.
Alex Williamson (1):
KVM: MTRR: Use default type for non-MTRR-covered gfn before WARN_ON
Christian Borntraeger (1):
KVM: s390: Fix hang VCPU hang/loop regression
Paolo Bonzini (1):
Merge tag 'kvm-s390-master-20150730' of
git
-off-by: Steve Rutherford srutherf...@google.com
Suggested-by: Andrew Honig aho...@google.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Documentation/virtual/kvm/api.txt | 17 +
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/i8254.c | 4 +++-
arch/x86
Unit Tests.
Signed-off-by: Steve Rutherford srutherf...@google.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Documentation/virtual/kvm/api.txt | 14 +
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/irq.c| 32 +++--
arch/x86
-off-by: Paolo Bonzini pbonz...@redhat.com
---
Documentation/virtual/kvm/api.txt | 9 ++---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/ioapic.h | 2 ++
arch/x86/kvm/irq_comm.c | 42 +++
arch/x86/kvm/lapic.c | 3
tested for Intel x86.
Signed-off-by: Steve Rutherford srutherf...@google.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Documentation/virtual/kvm/api.txt | 12
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/lapic.c | 24 +---
arch/x86
Avoid pointer chasing and memory barriers, and simplify the code
when split irqchip (LAPIC in kernel, IOAPIC/PIC in userspace)
is introduced.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/irq.c | 6 +++---
arch/x86/kvm/irq.h | 8
arch/x86/kvm/lapic.c | 4
This will avoid an unnecessary trip to -kvm and from there to the VPIC.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/kvm/irq.c | 2 +-
arch/x86/kvm/lapic.c| 4 ++--
arch/x86/kvm/lapic.h| 4 ++--
arch
/KVM_EXIT_IRQ_WINDOW_OPEN for dm_request_for_irq_injection).
However, dm_request_for_irq_injection is basically dead code! Revive it
by removing the checks in vmx.c and svm.c's vmexit handlers, and
fixing the returned values for the dm_request_for_irq_injection case.
Signed-off-by: Paolo Bonzini pbonz
I am going to push the memory barrier fixes to kvm/next.
The rest of the series is here for review. This includes cleanups from
myself and the bulk of the code from Steve.
Paolo
Paolo Bonzini (5):
KVM: x86: set TMR when the interrupt is accepted
KVM: x86: store IOAPIC-handled vectors
Do not compute TMR in advance. Instead, set the TMR just before the interrupt
is accepted into the IRR. This limits the coupling between IOAPIC and LAPIC.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/ioapic.c | 9 ++---
arch/x86/kvm/ioapic.h | 3 +--
arch/x86/kvm
for these interrupts anyway.
This again limits the interactions between the IOAPIC and the LAPIC,
making it easier to move the former to userspace.
Inspired by a patch from Steve Rutherford.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/asm/kvm_host.h | 3 ++-
arch/x86/kvm
On 05/08/2015 18:33, Radim Krčmář wrote:
The guest can use KVM_USER_EXIT instead of a signal-based exiting to
userspace. Availability depends on KVM_CAP_USER_EXIT.
Only x86 is implemented so far.
Signed-off-by: Radim Krčmář rkrc...@redhat.com
---
v2:
* use vcpu ioctl instead of vm
On 05/08/2015 18:48, Nicholas Krause wrote:
This fixes the error handling in the function vgic_v3_probe
for when calling the function kvm_register_device_ops to check
if the call to this function has returned a error code and if
so jump to the label out with goto to cleanup no longer
On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can be
inferred from the IOAPIC routes but the TMR cannot. The hardware
behavior on the other hand can be implemented purely within the LAPIC.
So updating the TMR within LAPIC is the
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev support
then we should target using pci to expose it. I'm ok with that,
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev support
then we should target using pci to expose it. I'm ok with that,
On 04/08/2015 12:59, Xiao Guangrong wrote:
+/*
+ * the page table on host is the shadow page table for the page
+ * table in guest or amd nested guest, its mmu features completely
+ * follow the features in guest.
+ */
+void
+reset_shadow_rsvds_bits_mask(struct kvm_vcpu *vcpu, struct
On 04/08/2015 15:10, Xiao Guangrong wrote:
This should be cpu_has_nx, I think.
cpu_has_nx() checks the feature on host CPU, however, this is the shadow
page table which completely follow guest's features.
E.g, if guest does not execution-protect the physical page, then
KVM does not do
On 03/08/2015 04:37, Zhang, Yang Z wrote:
Only virtualized APIC register reads use the virtual TMR registers (SDM
29.4.2 or 29.5), but these just read data from the corresponding field
in the virtual APIC page.
24.11.4 Software Access to Related Structures
In addition to data in the
On 03/08/2015 12:23, Zhang, Yang Z wrote:
In any case, the TMR behavior introduced by the APICv patches is
completely different from the hardware behavior, so it has to be fixed.
But any real problem with it?
It is a problem for split irqchip, where the EOI exit bitmap can be
inferred
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
Why not use virtio-mmio + testdev on ppc as well? Similar to how we're
not using PSCI on ARM or ACPI on x86.
Paolo
--
To
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
Why not use virtio-mmio + testdev on ppc as well? Similar to how we're
not using PSCI on ARM or ACPI on x86.
Paolo
--
To
On 03/08/2015 16:41, Andrew Jones wrote:
This series is the first series of a series of series that will
bring support to kvm-unit-tests for ppc64, and eventually ppc64le.
(Yes, the word 'series' is four times in that sentence. And now I've
typed 'series' five times! Wait, now six times! OK,
On 03/08/2015 16:41, Andrew Jones wrote:
This series is the first series of a series of series that will
bring support to kvm-unit-tests for ppc64, and eventually ppc64le.
(Yes, the word 'series' is four times in that sentence. And now I've
typed 'series' five times! Wait, now six times! OK,
On 01/08/2015 23:20, Bandan Das wrote:
Actually it should be using the RTC alarm to wake itself up. But the
firmware changed recently and the ACPI PMBASE moved from 0xb000 to
0x600. Try this (untested):
Ah thanks! your patch works for me. Is this one of the static entries in
the ACPI
On 01/08/2015 21:05, Bandan Das wrote:
Shih-Wei Li shih...@cs.columbia.edu writes:
Hi Paolo,
I've tried to apply the patch, and found that it passed most of the
problematic tests I mentioned earlier (IPI related, kvmclock_test).
However, it stopped still at s3 and couldn't finish it. Do
On 31/07/2015 17:06, Alex Bennée wrote:
I haven't seen this upstream yet. Has this been pushed yet?
Nope...
Paolo
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
More majordomo info at
On 31/07/2015 01:08, Pavel Shirshov wrote:
Hello,
Today I was very surprised to see that KVM with enabled HugePages uses
much more memory versus KVM without HugePages enabled.
I have a server with 386Gb memory.
I have a VM image which allocate up to 3.2Gb memory (libvirt memory/ tag).
On 31/07/2015 04:49, Steve Rutherford wrote:
Oh... Yeah. That's a damn good point, given that the interrupt can be
injected from another thread while one is in that guest vcpu.
Easiest time to update the TMR should be on guest entry through
vcpu_scan_ioapic, as before.
The best way to
On 31/07/2015 01:26, Zhang, Yang Z wrote:
Do not compute TMR in advance. Instead, set the TMR just before
the interrupt is accepted into the IRR. This limits the coupling
between IOAPIC and LAPIC.
Uh.., it back to original way which is wrong. You cannot modify the
apic page(here is the
Test the undocumented ICEBP (aka INT1 or INT01) opcode, and test that
dr6.BS is not modified by neither watchpoints nor breakpoints.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/debug.c | 51 ---
1 file changed, 44 insertions(+), 7
On 30/07/2015 06:41, Bandan Das wrote:
diff --git a/x86/cstart64.S b/x86/cstart64.S
index 8d0d95d..8d5ee2d 100644
--- a/x86/cstart64.S
+++ b/x86/cstart64.S
@@ -213,7 +213,11 @@ idt_descr:
load_tss:
lidtq idt_descr
- mov $0, %eax
+ mov $0x10, %eax
+ mov
On 30/07/2015 13:40, Christian Borntraeger wrote:
+ /* Pairs with smp_wmb() in kvm_vm_ioctl_create_vcpu, in case
+ * the caller has read kvm-online_vcpus before (as is the case
+ * for kvm_for_each_vcpu, for example).
+ */
smp_rmb();
Hmmm, wouldnt something like
-by: Shih-Wei Li shih...@cs.columbia.edu
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/cstart64.S | 6 --
1 file changed, 6 deletions(-)
diff --git a/x86/cstart64.S b/x86/cstart64.S
index 8d5ee2d..e947888 100644
--- a/x86/cstart64.S
+++ b/x86/cstart64.S
@@ -213,12 +213,6 @@ idt_descr
On 30/07/2015 15:57, Christian Borntraeger wrote:
+ /* Pairs with smp_wmb() in kvm_vm_ioctl_create_vcpu, in case
+ * the caller has read kvm-online_vcpus before (as is the case
+ * for kvm_for_each_vcpu, for example).
+ */
is somewhat distracting because of read and before. So something
On 30/07/2015 13:51, kbuild test robot wrote:
tree: git://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
head: 50079e2c9bcb2dd8ffe573c0edddbef9ad6fd809
commit: b7b0d2b2f35c0e6882ea0b342318bf06472ce756 [25/26] KVM: x86: Add EOI
exit bitmap inference
config: mips-jz4740 (attached as
On 30/07/2015 13:22, Christian Borntraeger wrote:
static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu)
{
- if (!vcpu-requests)
- return 0;
retry:
kvm_s390_vcpu_request_handled(vcpu);
+ if (!vcpu-requests)
+ return 0;
/*
Should
On 30/07/2015 05:14, Steve Rutherford wrote:
+static void test_ioapic_level_retrigger(void)
+{
+ handle_irq(0x9a, ioapic_isr_9a);
+ set_ioapic_redir(0x0e, 0x9a, LEVEL_TRIGGERED);
+
+ asm volatile (cli);
+ set_irq_line(0x0e, 1);
+ while (g_isr_9a != 2)
+ asm
On 30/07/2015 08:32, Steve Rutherford wrote:
+u8 kvm_arch_nr_userspace_ioapic_pins(struct kvm *kvm);
#else
static inline void kvm_vcpu_request_scan_ioapic(struct kvm *kvm)
{
}
+static inline void kvm_arch_irq_routing_update(struct kvm *kvm)
+{
+}
+static inline u8
On 30/07/2015 08:21, Steve Rutherford wrote:
First patch in a series which enables the relocation of the
PIC/IOAPIC to userspace.
Adds capability KVM_CAP_SPLIT_IRQCHIP;
KVM_CAP_SPLIT_IRQCHIP enables the construction of LAPICs without the
rest of the irqchip.
Compile tested for x86.
On 30/07/2015 08:21, Steve Rutherford wrote:
Architectures: x86, ppc, mips
Type: vcpu ioctl
Parameters: struct kvm_interrupt (in)
-Returns: 0 on success, -1 on error
+Returns: 0 on success, negative on failure.
Really returns -1 because...
-Queues a hardware interrupt vector to be
On 30/07/2015 05:55, Steve Rutherford wrote:
static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
{
- u64 eoi_exit_bitmap[4];
-
if (!kvm_apic_hw_enabled(vcpu-arch.apic))
return;
- memset(eoi_exit_bitmap, 0, 32);
+ memset(vcpu-arch.eoi_exit_bitmap, 0,
On 30/07/2015 05:32, Steve Rutherford wrote:
+ /* Write kvm-irq_routing before kvm-arch.vpic. */
+ smp_wmb();
I assume this pairs with irqchip_in_kernel?
Yes, see the comment added there by this same patch (read
kvm-arch.vpic before kvm-irq_routing).
Paolo
--
To
On 29/07/2015 21:07, Alex Williamson wrote:
diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm/mtrr.c
index e275013..dc0a84a 100644
--- a/arch/x86/kvm/mtrr.c
+++ b/arch/x86/kvm/mtrr.c
@@ -672,15 +672,16 @@ u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu
*vcpu, gfn_t gfn)
if
On 30/07/2015 06:36, Steve Rutherford wrote:
On Wed, Jul 29, 2015 at 03:28:57PM +0200, Paolo Bonzini wrote:
The PIT is only created if irqchip_in_kernel returns true, so the
check is superfluous.
I poked around. Looks to me like the existence of an IOAPIC is not
checked on the creation
On 30/07/2015 10:37, Steve Rutherford wrote:
This looks a bit non-sensical, but is overprepared for the introduction
IOAPIC hotplug, which two patches down the line. Changing it is fine,
you'll just need to merge the very same change back.
By IOAPIC hotplug you mean changing the number of
On 30/07/2015 08:21, Steve Rutherford wrote:
*/
int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
{
- if (!irqchip_in_kernel(v-kvm))
+ if (!pic_in_kernel(v-kvm))
return v-arch.interrupt.pending;
if (kvm_cpu_has_extint(v))
@@ -75,7 +88,7 @@ int
This optimizes a little the code with split irqchip, by avoiding the
need to check both vcpu-kvm-arch.vpic and vcpu-kvm-irqchip_split.
No conflicts with Steve's patches, except for the irq.c hunks that I
have commented on earlier.
Paolo
Paolo Bonzini (2):
KVM: x86: replace vm_has_apicv hook
Avoid pointer chasing and memory barriers, and simplify the code
when split irqchip (LAPIC in kernel, IOAPIC/PIC in userspace)
is introduced.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/irq.c | 6 +++---
arch/x86/kvm/irq.h | 8
arch/x86/kvm/lapic.c | 4
/KVM_EXIT_IRQ_WINDOW_OPEN for dm_request_for_irq_injection).
However, dm_request_for_irq_injection is basically dead code! Revive it
by removing the checks in vmx.c and svm.c's vmexit handlers, and
fixing the returned values for the dm_request_for_irq_injection case.
Signed-off-by: Paolo Bonzini pbonz
This will avoid an unnecessary trip to -kvm and from there to the VPIC.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/kvm/irq.c | 2 +-
arch/x86/kvm/lapic.c| 4 ++--
arch/x86/kvm/lapic.h| 4 ++--
arch
On 29/07/2015 06:49, Venkatesh Srinivas wrote:
You can call it even feature^Wbug, I won't take it personal. :) It does
not prevent scary messages (such as intel_rapl: no valid rapl domains
found in package 0) in the logs for example. See
https://bugzilla.redhat.com/show_bug.cgi?id=1178491
On 29/07/2015 11:19, Peter Zijlstra wrote:
On Tue, Jul 28, 2015 at 05:23:22PM -0700, Andy Lutomirski wrote:
PeterZ, can we fix this for real instead of relying on
CONFIG_PARAVIRT=y accidentally turning all msr accesses into safe
accesses? We have the CPUID hypervisor bit, but I still don't
On 29/07/2015 11:40, Peter Zijlstra wrote:
Well, people have complained about it because it's KERN_ERR. Do you
think it is okay to downgrade this (perhaps not even just on VMs) to info?
Ah, do people really have nothing better to do? ;-) Seems like a petty
complaint.
Sure, it seems
On 28/07/2015 21:06, Steve Rutherford wrote:
+static inline int pic_in_kernel(struct kvm *kvm)
+{
+ int ret;
+
+ ret = (pic_irqchip(kvm) != NULL);
+ smp_rmb();
What does this memory barrier pair with? I don't think it's necessary.
To be honest, it's
On 29/07/2015 11:05, Christian Borntraeger wrote:
Paolo,
this time only some small changes for s390, mostly serviceability
changes and small fixes/optimizations.
Christian
The following changes since commit 5492830370171b6a4ede8a3bfba687a8d0f25fa5:
KVM: svm: handle
On 28/07/2015 01:17, Steve Rutherford wrote:
+
+ if (irqchip_in_kernel(vcpu-kvm) !pic_in_kernel(vcpu-kvm)
+ vcpu-arch.pending_external_vector == -1) {
+ vcpu-arch.pending_external_vector = irq-irq;
+ return 0;
+ } else if
This is another remnant of ia64 support.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/asm/kvm_host.h | 3 +++
arch/x86/kvm/x86.c | 20
include/linux/kvm_host.h| 16
virt/kvm/kvm_main.c | 14
On 28/07/2015 01:17, Steve Rutherford wrote:
First patch in a series which enables the relocation of the
PIC/IOAPIC to userspace.
Adds capability KVM_CAP_SPLIT_IRQCHIP;
KVM_CAP_SPLIT_IRQCHIP enables the construction of LAPICs without the
rest of the irqchip.
Compile tested for x86.
for these interrupts anyway.
This again limits the interactions between the IOAPIC and the LAPIC,
making it easier to move the former to userspace.
Inspired by a patch from Steve Rutherford.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/asm/kvm_host.h | 3 ++-
arch/x86/kvm
of irqchip_in_kernel do not need the barrier and they
could check vcpu-arch.apic instead of vcpu-kvm-arch.pic. I plan to
change that by introducing lapic_in_kernel(struct kvm_vcpu *), after
the split irqchip patches are in which will make irqchip_in_kernel more
expensive.
Paolo
Paolo Bonzini (4
Test resampling of level interrupts after EOI, by leaving the IRQ
line set in the ISR. One tests does reset the IRQ line after a while,
the other uses masking instead in the ISR.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/ioapic.c | 51
kvm_pic* and reuse it if the IOAPIC creation fails.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/i8259.c | 15 +--
arch/x86/kvm/irq.h | 8
arch/x86/kvm/x86.c | 17 ++---
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/x86
There is no smp_rmb matching the smp_wmb. shared_msr_update is called from
hardware_enable, which in turn is called via on_each_cpu. on_each_cpu
and must imply a read memory barrier (on x86 the rmb is achieved simply
through asm volatile in native_apic_mem_write).
Signed-off-by: Paolo Bonzini
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/linux/kvm_host.h | 4
virt/kvm/kvm_main.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index bd1097a95704..81089cf1f0c1 100644
--- a/include/linux/kvm_host.h
+++ b
The PIT is only created if irqchip_in_kernel returns true, so the
check is superfluous.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/i8254.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index f90952f64e79
Applied as follows:
+Maintainers
+---
+M: Paolo Bonzini pbonz...@redhat.com
+M: Marcelo Tosatti mtosa...@redhat.com
+L: kvm@vger.kernel.org
+T: git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git
+
+Architecture Specific Code:
+---
+
+ARM
+M: Drew
On 29/07/2015 16:56, Michael S. Tsirkin wrote:
Also, document our contract with legacy userspace: when running on an
old kernel, you get -1 and you can assume at least 64 slots. Since 0
value's left unused, let's make that mean that the current userspace
behaviour (trial and
On 13/07/2015 19:02, Andrew Jones wrote:
Add support to convert unit tests to standalone scripts that
can be run outside the framework. This is almost an RFC, but
it doesn't impact the current framework (except for 'make install',
but was that ever used?). The scripting is ugly, but I see
On 24/07/2015 14:07, Andrew Jones wrote:
@@ -58,6 +59,7 @@ void phys_alloc_set_minimum_alignment(phys_addr_t align)
static phys_addr_t phys_alloc_aligned_safe(phys_addr_t size,
phys_addr_t align, bool safe)
{
+ static bool not_warned = true;
I
On 27/07/2015 09:54, Andrew Jones wrote:
Also, please rename to tlbflush-test.c to differentiate it
from an implementation of tlbflush support, and to make
the standalone test name (if we commit those patches) more
descriptive.
I disagree here. Support code would go in lib/arm.
As we're
On 29/07/2015 09:39, Andrew Jones wrote:
Easy addition to the devicetree support that may come in handy
for powerpc (and it may not - I have a ppc series ready to post
that doesn't actually bother with stdout-path yet, but whatever...)
For v2 I decided it's better to return
On 28/07/2015 01:17, Steve Rutherford wrote:
diff --git a/arch/x86/kvm/ioapic.h b/arch/x86/kvm/ioapic.h
index d8cc54b..f6ce112 100644
--- a/arch/x86/kvm/ioapic.h
+++ b/arch/x86/kvm/ioapic.h
@@ -9,6 +9,7 @@ struct kvm;
struct kvm_vcpu;
#define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
Do not compute TMR in advance. Instead, set the TMR just before the interrupt
is accepted into the IRR. This limits the coupling between IOAPIC and LAPIC.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/kvm/ioapic.c | 9 ++---
arch/x86/kvm/ioapic.h | 3 +--
arch/x86/kvm
a userspace IOAPIC.
Tested with ioapic.flat for now, planning to do more complete tests
tomorrow. The most interesting test to do here is an assigned device
that uses INTX, so I am CCing Alex Williamson for a heads up.
Paolo
Paolo Bonzini (2):
KVM: x86: set TMR when the interrupt is accepted
On 28/07/2015 10:56, Alex Bennée wrote:
+Architecture Specific Code:
+---
+
+ARM
+M: Christoffer Dall christoffer.d...@linaro.org
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+L: kvm...@lists.cs.columbia.edu
+F: arm/*
+
Hmm, shouldn't
On 27/07/2015 20:45, Andy Lutomirski wrote:
On Mon, Jul 27, 2015 at 11:30 AM, Paolo Bonzini pbonz...@redhat.com wrote:
On 27/07/2015 19:51, Andy Lutomirski wrote:
I think I'm missing something. Does KVM_GUEST hook read_msr and
write_msr? I don't see it.
PARAVIRT does, and it's the main
On 28/07/2015 01:17, Steve Rutherford wrote:
return kvm-arch.vpic;
}
+static inline int pic_in_kernel(struct kvm *kvm)
+{
+ int ret;
+
+ ret = (pic_irqchip(kvm) != NULL);
+ smp_rmb();
What does this memory barrier pair with? I don't think it's necessary.
+
On 28/07/2015 21:06, Steve Rutherford wrote:
+ if (!kvm_run-ready_for_interrupt_injection
+ ready_for_interrupt_injection)
+ kvm_make_request(KVM_REQ_PIC_UNMASK_EXIT, vcpu);
+
+
On 24/07/2015 19:33, Andy Lutomirski wrote:
PARAVIRT adds a fair amount of bloat and, AFAICT, KVM_GUEST doesn't
really need any of it. Would it make sense to drop the dependency?
I think the main reason for PARAVIRT is that pv kernels have by default
.read_msr =
On 27/07/2015 17:56, Andy Lutomirski wrote:
On Mon, Jul 27, 2015 at 6:59 AM, Paolo Bonzini pbonz...@redhat.com wrote:
On 24/07/2015 19:33, Andy Lutomirski wrote:
PARAVIRT adds a fair amount of bloat and, AFAICT, KVM_GUEST doesn't
really need any of it. Would it make sense to drop
On 27/07/2015 19:51, Andy Lutomirski wrote:
I think I'm missing something. Does KVM_GUEST hook read_msr and
write_msr? I don't see it.
PARAVIRT does, and it's the main reason why you'd want PARAVIRT for a
KVM guest.
Still confused. On a KVM guest (with PARAVIRT=y), doesn't
to the quirks API
* extending one of the quirks from just AMD to Intel as well, because
4.2 can show the same problem with problematic firmware on Intel too.
Paolo Bonzini (2):
KVM: x86: introduce kvm_check_has_quirk
KVM: x86
On 16/07/2015 06:10, Alex Williamson wrote:
On Thu, 2015-07-16 at 03:25 +0800, Xiao Guangrong wrote:
From: Xiao Guangrong guangrong.x...@intel.com
Currently code uses default memory type if MTRR is fully disabled,
fix it by using UC instead
Signed-off-by: Xiao Guangrong
Make them clearly architecture-dependent; the capability is valid for
all architectures, but the argument is not.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
arch/x86/include/uapi/asm/kvm.h | 4 ++--
arch/x86/kvm/lapic.c| 2 +-
arch/x86/kvm/svm.c | 2 +-
arch
On 23/07/2015 08:29, Xiao Guangrong wrote:
In fact this is the same quirk already implemented for SVM as
KVM_QUIRK_CD_NW_CLEARED, so we can reuse the bit.
Sounds good to me. I will drop the new bit and reuse as your suggestion.
And i think we need document this whole staff in API.txt ...
-bit mode, for both
the BSP and the APs.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
x86/cstart64.S | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/x86/cstart64.S b/x86/cstart64.S
index 8d0d95d..8d5ee2d 100644
--- a/x86/cstart64.S
+++ b/x86/cstart64.S
@@ -213,7
On 21/07/2015 15:55, Vlastimil Babka wrote:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2d73807..a8723a8 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3158,7 +3158,7 @@ static struct vmcs *alloc_vmcs_cpu(int cpu)
struct page *pages;
struct vmcs
On 15/07/2015 21:25, Xiao Guangrong wrote:
From: Xiao Guangrong guangrong.x...@intel.com
Current firmware depends on WB to fast boot, please refer to
https://lkml.org/lkml/2015/7/12/115
Let's us WB if CR0.CD is set to make this kind of firmware happy
This quirk can be dropped by
On 17/07/2015 09:27, Pavel Fedin wrote:
+ } else if (!msi-flags)
+ return -EINVAL;
Did you mean if (msg-flags) here (inverted condition)?
Indeed, and also you need { } around the return for the QEMU coding
standard.
Paolo
+
+ /* historically the route.type was not set */
Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: kvm@vger.kernel.org
Cc: qemu-sta...@nongnu.org
Message-Id: 1429871214-23514-3-git-send-email-james.ho...@imgtec.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-mips/kvm.c | 8
Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: kvm@vger.kernel.org
Cc: qemu-sta...@nongnu.org
Message-Id: 1429871214-23514-2-git-send-email-james.ho...@imgtec.com
Signed-off-by: Paolo Bonzini pbonz
On 15/07/2015 22:02, C. Bröcker wrote:
What OS is this? Is it RHEL/CentOS? If so, halt_poll_ns will be in 6.7
which will be out in a few days/weeks.
Paolo
OK. As said CentOS 6.6.
But where do I put this parameter?
You can add kvm.halt_poll_ns=50 to the kernel command line. If
you
, PPC,
etc).
It seems like this problem is limited to pre-Haswell EPT.
I'm okay with the patch. If we find problems later we can always add a
parameter to kvm_age_hva so that it effectively doesn't do anything on
clear_young.
Acked-by: Paolo Bonzini pbonz...@redhat.com
Paolo
--
To unsubscribe
Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: kvm@vger.kernel.org
Cc: qemu-sta...@nongnu.org
Message-Id: 1429871214-23514-2-git-send-email-james.ho...@imgtec.com
Signed-off-by: Paolo Bonzini pbonz
Bonzini pbonz...@redhat.com
Cc: Leon Alrae leon.al...@imgtec.com
Cc: Aurelien Jarno aurel...@aurel32.net
Cc: kvm@vger.kernel.org
Cc: qemu-sta...@nongnu.org
Message-Id: 1429871214-23514-3-git-send-email-james.ho...@imgtec.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-mips/kvm.c | 8
On 17/07/2015 02:35, Andy Lutomirski wrote:
Right now, NPT page attributes are not used, and the final page
attribute depends solely on gPAT (which however is not synced
correctly), the guest MTRRs and the guest page attributes.
However, we can do better by mimicking what is done for VMX.
.
Jan Kiszka (1):
KVM: SVM: Sync g_pat with guest-written PAT value
Paolo Bonzini (5):
x86: hyperv: add CPUID bit for crash handlers
KVM: x86: reintroduce kvm_is_mmio_pfn
KVM: count number of assigned devices
KVM: SVM: use
The long delay that Alex reported (for the case when all guest memory
was set to UC up-front) is due to the fact that the SEC phase of OVMF
decompresses an approximately 1712 KB sized, LZMA-compressed blob, to
approx. 896 KB worth of PEI drivers and 8192 KB worth of DXE and UEFI
drivers --
On 13/07/2015 12:25, Andre Przywara wrote:
For using MSIs in a guest when running on an ARM(64) system using a
GICv3 interrupt controller we need to have a device ID available. On
real hardware this information is sampled from the bus by the ITS part
of the interrupt controller.
To make
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