Qemu e1000 NIC didn't work well for guest windows on xen/ia64.
After investigation, it's a e1000 TSE bug.
Previously, all data descriptors used TSE context descriptor by default,
It's not correct, per spec, data descriptor uses TSE bit to indicate
whether use TSE,
Legacy data descripter never use
Hi Jes,
You can use this one, I'm considering how to make it more generic per
AVI comment.
Anthony
Jes Sorensen wrote:
Hi Anthony,
Looking back through this thread - do you happen to have an updated
patch for the irq problem? If not, could you let me know which is your
latest version and
From 67806cc642cb666fb59fec60115fee37b80ecb3a Mon Sep 17 00:00:00 2001
From: Anthony Xu [EMAIL PROTECTED]
Date: Wed, 18 Jun 2008 14:32:46 -0400
Subject: [PATCH] Irq assignment
1. use bimodal _PRT
2. pci device can use irq 15, reduce interrupt sharing
3. test by running linux guest in kvm-ia64,
From 7b2c2612b21b895cd14e632fea845c03b6e1dedc Mon Sep 17 00:00:00 2001
From: Anthony Xu [EMAIL PROTECTED]
Date: Thu, 29 May 2008 13:14:56 -0400
Subject: [PATCH] Make qemu compile for kvm-ia64
Since merging with Qemu upsteram, it can't be compiled
for kvm-ia64
Signed-off-by: Anthony Xu [EMAIL
Marcelo Tosatti wrote:
On Fri, Jun 13, 2008 at 12:15:23AM +0800, Xu, Anthony wrote:
I think it would be better to avoid static PCI pin - IOAPIC pin
assignments, if PCI link devices can be used (allowing the OS to
route IRQ's as it wishes to).
Seems PCI link device only support irq-pin 16
From: Alexander Graf [mailto:[EMAIL PROTECTED]
Sent: 2008年6月13日 22:31
To: Xu, Anthony
Cc: Avi Kivity; Marcelo Tosatti; Jes Sorensen; kvm@vger.kernel.org; [EMAIL
PROTECTED]
Subject: Re: [RFC] kvm irq assignment
On Jun 12, 2008, at 11:38 PM, Xu, Anthony
Avi Kivity wrote:
Xu, Anthony wrote:
Hi Avi and all
This is the revised one,
All PCI devices send interrupt to both PIC and IOAPIC,
a). When PIC is enabled and IOAPIC is disabled, all redirect
entries in IOAPIC are masked. B) When PIC is disabled and IPAPIC is
enabled, link entry bit7
;
pci_dev = bus-parent_dev;
Xu, Anthony wrote:
Marcelo Tosatti wrote:
Hi Anthony,
On Fri, Jun 13, 2008 at 02:38:08PM +0800, Xu, Anthony wrote:
Hi Avi and all
This is the revised one,
All PCI devices send interrupt to both PIC and IOAPIC,
a). When PIC is enabled and IOAPIC
.
For KVM/IA64, only two functions ioapic_map_irq and ioapic_set_irq are needed,
and
Native qemu doesn't support guest IA64 platform yet.
So, the simple way is to put these two functions in ia64 specific file, ipf.c
Thanks,
Anthony
Xu, Anthony wrote:
From
: optimize */
pic_irq = piix3_dev-config[0x60 + irq_num];
+/* if bit7 set 1, this link is disabled */
+if (pic_irq 0x80)
+return;
if (pic_irq 16) {
/* The pic level is the logical OR of all the PCI irqs mapped
to it */
Xu, Anthony wrote:
Avi Kivity
Alexander Graf wrote:
On Jun 10, 2008, at 12:57 AM, Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch
about irq assignment, can you post it in this thread again, thx?
I'll attach it to this mail.
This patch is stilling use legacy
Marcelo Tosatti wrote:
On Tue, Jun 10, 2008 at 03:57:30PM +0800, Xu, Anthony wrote:
diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
index a23a466..df0ea33 100644
--- a/qemu/hw/pci.c
+++ b/qemu/hw/pci.c
@@ -548,7 +548,7 @@ static void pci_set_irq(void *opaque, int
irq_num, int level
Avi Kivity wrote:
Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch
about irq assignment, can you post it in this thread again, thx?
Below patch makes all PCI devices use level-trigger , active low
interrupt, it worked well when
Hi all,
Thanks for your comments.
I made this new patch based on your comments
1. use bimodal _PRT, to take advantage of IOAPIC pin 16~23
the mapping is simple, slot - (slot7)+16 IOAPIC pin,
someone may provide good mapping ?
2. use ISA-bridge configure space 0x64 byte as a
Avi Kivity wrote:
I suggest modifying the firmware to report the interrupts as active
high. Since Xen does not emulate polarity, the change will not affect
it and the firmware can continue to be shared. I'd also recommend
fixing Xen to emulate the polarity correctly, if possible.
Thanks
In kvm-ia64, PCI devices use 48-pin virtual IOAPIC to deliver interrup.
Signed-off-by: Anthony Xu [EMAIL PROTECTED]
diff --git a/qemu/hw/piix_pci.c b/qemu/hw/piix_pci.c
index 90cb3a6..797ece7 100644
--- a/qemu/hw/piix_pci.c
+++ b/qemu/hw/piix_pci.c
@@ -28,6 +28,7 @@
typedef uint32_t
Avi Kivity wrote:
With 24 free pins, that's fine. With 8 free pins, less so. We'll
need to mix in more high bits.
I guess we need to increase the number of pins on x86 too.
If use this method, we can share same IA64 guest BIOS between
XEN/IA64 and KVM/IA64.
You can use this
Avi Kivity wrote:
x86 and ia64 have different DSDTs, so I don't see the need for dynamic
generation. The x86 DSDT can return different routing tables
depending
on whether one or two ioapics are present (this can be detected at
runtime).
Okay, use fixed DSDT
- Anthony
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