Hi Anthony,
Looking back through this thread - do you happen to have an updated
patch for the irq problem? If not, could you let me know which is your
latest version and I will try and look at it.
Cheers,
Jes
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Hi Jes,
You can use this one, I'm considering how to make it more generic per
AVI comment.
Anthony
Jes Sorensen wrote:
Hi Anthony,
Looking back through this thread - do you happen to have an updated
patch for the irq problem? If not, could you let me know which is your
latest version and
Marcelo Tosatti wrote:
On Fri, Jun 13, 2008 at 12:15:23AM +0800, Xu, Anthony wrote:
I think it would be better to avoid static PCI pin - IOAPIC pin
assignments, if PCI link devices can be used (allowing the OS to
route IRQ's as it wishes to).
Seems PCI link device only support irq-pin 16,
Alexander Graf wrote:
Apparently this is broken on x86 too. I was just trying this patch
with Mac OS X as target and magically the in-kernel APIC starts
working, so I guess something is going wrong already here.
Btw, according to the ACPI tables, all PCI interrupts are currently
defined
Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch about
irq assignment, can you post it in this thread again, thx?
Below patch makes all PCI devices use level-trigger , active low
interrupt, it worked well when running linux guest, I didn't
Alexander Graf wrote:
On Jun 10, 2008, at 12:57 AM, Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch
about irq assignment, can you post it in this thread again, thx?
I'll attach it to this mail.
This patch is stilling use legacy
Marcelo Tosatti wrote:
On Tue, Jun 10, 2008 at 03:57:30PM +0800, Xu, Anthony wrote:
diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
index a23a466..df0ea33 100644
--- a/qemu/hw/pci.c
+++ b/qemu/hw/pci.c
@@ -548,7 +548,7 @@ static void pci_set_irq(void *opaque, int
irq_num, int level)
Avi Kivity wrote:
Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch
about irq assignment, can you post it in this thread again, thx?
Below patch makes all PCI devices use level-trigger , active low
interrupt, it worked well when
On Jun 10, 2008, at 12:57 AM, Xu, Anthony wrote:
Thanks for comments
Basically we are on the same page, while I didn't find your patch
about
irq assignment, can you post it in this thread again, thx?
I'll attach it to this mail.
Below patch makes all PCI devices use level-trigger ,
Avi Kivity wrote:
I suggest modifying the firmware to report the interrupts as active
high. Since Xen does not emulate polarity, the change will not affect
it and the firmware can continue to be shared. I'd also recommend
fixing Xen to emulate the polarity correctly, if possible.
Thanks
On Jun 10, 2008, at 8:33 AM, Xu, Anthony wrote:
Avi Kivity wrote:
I suggest modifying the firmware to report the interrupts as active
high. Since Xen does not emulate polarity, the change will not
affect
it and the firmware can continue to be shared. I'd also recommend
fixing Xen to
Avi Kivity wrote:
Xu, Anthony wrote:
In kvm-ia64, we use the same guest firmware (GFW)as in Xen, GFW uses
PRT to present PCI interrupt routing, all PCI devices'
interrupt pins
connect to IOAPIC, which doesn't match with kvm-ia64 Qemu PCI interrupt
routing.
This patch modify Qemu PCI interupt
Xu, Anthony wrote:
In kvm-ia64, we use the same guest firmware (GFW)as in Xen,
GFW uses PRT to present PCI interrupt routing, all PCI devices'
interrupt pins
connect to IOAPIC, which doesn't match with kvm-ia64 Qemu PCI interrupt
routing.
This patch modify Qemu PCI interupt routing code to
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