On Tue, Jul 21, 2015 at 09:16:57AM +0800, Shannon Zhao wrote:
>
>
> On 2015/7/17 18:21, Christoffer Dall wrote:
> > On Fri, Jul 17, 2015 at 04:45:44PM +0800, Shannon Zhao wrote:
> >>
> >>
> >> On 2015/7/17 3:55, Christoffer Dall wrote:
> >>> On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@
On 2015/7/17 18:21, Christoffer Dall wrote:
> On Fri, Jul 17, 2015 at 04:45:44PM +0800, Shannon Zhao wrote:
>>
>>
>> On 2015/7/17 3:55, Christoffer Dall wrote:
>>> On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote:
From: Shannon Zhao
Add reset handler which g
On Fri, Jul 17, 2015 at 04:45:44PM +0800, Shannon Zhao wrote:
>
>
> On 2015/7/17 3:55, Christoffer Dall wrote:
> > On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote:
> >> From: Shannon Zhao
> >>
> >> Add reset handler which gets host value of PMCR_EL0 and make writable
> >>
On 2015/7/17 3:55, Christoffer Dall wrote:
> On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote:
>> From: Shannon Zhao
>>
>> Add reset handler which gets host value of PMCR_EL0 and make writable
>> bits architecturally UNKNOWN. Add access handler which emulates
>> writing an
On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote:
> From: Shannon Zhao
>
> Add reset handler which gets host value of PMCR_EL0 and make writable
> bits architecturally UNKNOWN. Add access handler which emulates
> writing and reading PMCR_EL0 register.
>
> Signed-off-by: Sh
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN. Add access handler which emulates
writing and reading PMCR_EL0 register.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 41 +++
