On Wed, May 21, 2014 at 11:02:12PM +0200, Andreas Herrmann wrote:
On Wed, May 21, 2014 at 02:40:41PM +0200, Ralf Baechle wrote:
On Tue, May 20, 2014 at 04:47:07PM +0200, Andreas Herrmann wrote:
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+
On 20/05/14 15:47, Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
On Tue, May 20, 2014 at 04:47:07PM +0200, Andreas Herrmann wrote:
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+ R4600_HIT_CACHEOP_WAR_IMPL;
The R4600 has 32 byte cache lines that is this line will never be
executed on an R4600 thus can be dropped.
+
On 05/21/2014 03:04 AM, James Hogan wrote:
On 20/05/14 15:47, Andreas Herrmann wrote:
From: David Daney david.da...@cavium.com
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann
On Wed, May 21, 2014 at 02:40:41PM +0200, Ralf Baechle wrote:
On Tue, May 20, 2014 at 04:47:07PM +0200, Andreas Herrmann wrote:
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+ R4600_HIT_CACHEOP_WAR_IMPL;
The R4600 has 32 byte cache lines that is this line
From: David Daney david.da...@cavium.com
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney david.da...@cavium.com
Signed-off-by: Andreas Herrmann andreas.herrm...@caviumnetworks.com
---
arch/mips/include/asm/r4kcache.h |2 ++
arch/mips/mm/c-r4k.c
