On 2015-02-10 17:18, Paolo Bonzini wrote:
On 10/02/2015 17:15, Jan Kiszka wrote:
#define CR3_L_MODE_RESERVED_BITS 0xFF00ULL
+#define CR3_PCID_INVD (1UL 63)
1ULL (for i386)
Already fixed:
commit cfaa790a3fb8a7efa98f4a6457e19dc3a0db35d3
Author: Borislav Petkov
On 2014-11-02 10:54, Nadav Amit wrote:
Although Intel SDM mentions bit 63 is reserved, MOV to CR3 can have bit 63
set.
As Intel SDM states in section 4.10.4 Invalidation of TLBs and
Paging-Structure Caches: MOV to CR3. ... If CR4.PCIDE = 1 and bit 63 of the
instruction’s source operand is 0
On 10/02/2015 17:15, Jan Kiszka wrote:
#define CR3_L_MODE_RESERVED_BITS 0xFF00ULL
+#define CR3_PCID_INVD (1UL 63)
1ULL (for i386)
Already fixed:
commit cfaa790a3fb8a7efa98f4a6457e19dc3a0db35d3
Author: Borislav Petkov b...@suse.de
Date: Thu Jan 15 09:44:56 2015
On 10/02/2015 17:34, Jan Kiszka wrote:
commit cfaa790a3fb8a7efa98f4a6457e19dc3a0db35d3
Author: Borislav Petkov b...@suse.de
Date: Thu Jan 15 09:44:56 2015 +0100
kvm: Fix CR3_PCID_INVD type on 32-bit
arch/x86/kvm/emulate.c: In function ‘check_cr_write’:
Although Intel SDM mentions bit 63 is reserved, MOV to CR3 can have bit 63 set.
As Intel SDM states in section 4.10.4 Invalidation of TLBs and
Paging-Structure Caches: MOV to CR3. ... If CR4.PCIDE = 1 and bit 63 of the
instruction’s source operand is 0 ...
In other words, bit 63 is not reserved.
