Il 02/11/2012 16:17, Gerd Hoffmann ha scritto:
> On 11/02/12 16:13, Paolo Bonzini wrote:
>>> >> Hi,
>>> >>
>>> I think deferring IRQ events to the point when the complete vmstate
>>> is loaded is the cleaner and more robust approach.
>>> >>
>>> >> Agree. Just schedule a bh in post_load.
On 11/02/12 16:13, Paolo Bonzini wrote:
>> Hi,
>>
>>> I think deferring IRQ events to the point when the complete vmstate
>>> is
>>> loaded is the cleaner and more robust approach.
>>
>> Agree. Just schedule a bh in post_load.
>> See also a229c0535bd336efaec786dd6e352a54e0a8187d
>
> No, it cannot
> Hi,
>
> > I think deferring IRQ events to the point when the complete vmstate
> > is
> > loaded is the cleaner and more robust approach.
>
> Agree. Just schedule a bh in post_load.
> See also a229c0535bd336efaec786dd6e352a54e0a8187d
No, it cannot a bh. Right now incoming migration is blockin
Hi,
> I think deferring IRQ events to the point when the complete vmstate is
> loaded is the cleaner and more robust approach.
Agree. Just schedule a bh in post_load.
See also a229c0535bd336efaec786dd6e352a54e0a8187d
cheers,
Gerd
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On 2012-11-02 15:53, Paolo Bonzini wrote:
> Il 30/10/2012 19:21, Jan Kiszka ha scritto:
Aren't we still dependent on the order of processing? If the APIC is
restored after the device, won't we get the same problem?
>>>
>>> Strictly speaking yes, but CPUs and APICs are always the first de
Il 30/10/2012 19:21, Jan Kiszka ha scritto:
> > > Aren't we still dependent on the order of processing? If the APIC is
> > > restored after the device, won't we get the same problem?
> >
> > Strictly speaking yes, but CPUs and APICs are always the first devices
> > to be saved.
> Hmm, thinking ab
On 2012-10-30 15:16, Paolo Bonzini wrote:
> Il 30/10/2012 13:38, Avi Kivity ha scritto:
>> On 10/30/2012 02:16 PM, Paolo Bonzini wrote:
>>> The LAPIC is loaded separately from the rest of the VCPU state. Thus,
>>> when restoring the CPU the dummy post-reset state is passed to the
>>> in-kernel API
On 2012-10-30 13:16, Paolo Bonzini wrote:
> The LAPIC is loaded separately from the rest of the VCPU state. Thus,
> when restoring the CPU the dummy post-reset state is passed to the
> in-kernel APIC.
>
> This can cause MSI injection to fail if attempted during the restore of
> another device, be
Il 30/10/2012 13:38, Avi Kivity ha scritto:
> On 10/30/2012 02:16 PM, Paolo Bonzini wrote:
>> The LAPIC is loaded separately from the rest of the VCPU state. Thus,
>> when restoring the CPU the dummy post-reset state is passed to the
>> in-kernel APIC.
>>
>> This can cause MSI injection to fail if
On 10/30/2012 02:16 PM, Paolo Bonzini wrote:
> The LAPIC is loaded separately from the rest of the VCPU state. Thus,
> when restoring the CPU the dummy post-reset state is passed to the
> in-kernel APIC.
>
> This can cause MSI injection to fail if attempted during the restore of
> another device,
The LAPIC is loaded separately from the rest of the VCPU state. Thus,
when restoring the CPU the dummy post-reset state is passed to the
in-kernel APIC.
This can cause MSI injection to fail if attempted during the restore of
another device, because the LAPIC believes it's not enabled.
Signed-off
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