Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-10 Thread Paolo Bonzini
Il 10/10/2014 03:55, Nadav Amit ha scritto: diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index b8345dd..51428dd 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1096,9 +1096,12 @@ static void start_apic_timer(struct kvm_lapic *apic) if

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-10 Thread Radim Krčmář
2014-10-10 11:45+0200, Paolo Bonzini: Il 10/10/2014 03:55, Nadav Amit ha scritto: diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index b8345dd..51428dd 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1096,9 +1096,12 @@ static void start_apic_timer(struct

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-10 Thread Nadav Amit
On Oct 10, 2014, at 12:45 PM, Paolo Bonzini pbonz...@redhat.com wrote: Il 10/10/2014 03:55, Nadav Amit ha scritto: diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index b8345dd..51428dd 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1096,9 +1096,12 @@ static void

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-10 Thread Paolo Bonzini
Il 10/10/2014 14:51, Nadav Amit ha scritto: Second, I think that the solution I proposed would perform better. Currently, there are many unnecessary cancellations and setups of the timer. This solution does not resolve this problem. I think it does. You do not get an hrtimer_start if

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-10 Thread Paolo Bonzini
Il 08/10/2014 12:06, Radim Krčmář ha scritto: KVM: x86: fix deadline tsc interrupt injection The check in kvm_set_lapic_tscdeadline_msr() was trying to prevent a situation where we lose a pending deadline timer in a MSR write. Losing it is fine, because it effectively occurs before the timer

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-09 Thread Nadav Amit
On Oct 8, 2014, at 1:06 PM, Radim Krčmář rkrc...@redhat.com wrote: And it would get one from the currently pending timer. What about the following patch? (The introduced else branch could use some abstractions.) --8--- KVM: x86: fix deadline tsc interrupt injection The check in

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-08 Thread Paolo Bonzini
Il 03/10/2014 00:10, Nadav Amit ha scritto: To solve this situation, ignore host initiated TSC deadline writes that do not change the deadline value. Signed-off-by: Nadav Amit na...@cs.technion.ac.il --- arch/x86/kvm/lapic.c | 7 ++- arch/x86/kvm/lapic.h | 3 ++- arch/x86/kvm/x86.c

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-08 Thread Radim Krčmář
2014-10-07 12:35+0300, Nadav Amit: Thanks for reviewing this patch and the rest of the gang. Happy to do so, I've learned a lot. On Oct 6, 2014, at 11:57 PM, Radim Krčmář rkrc...@redhat.com wrote: 2014-10-03 01:10+0300, Nadav Amit: Setting the TSC deadline MSR that are initiated by the

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-08 Thread Paolo Bonzini
Il 08/10/2014 12:06, Radim Krčmář ha scritto: - why is host_initiated required? Since if the guest writes to the MSR, it means it wants to rearm the TSC deadline. Even if the deadline passed, interrupt should be triggered. MSR isn't 0, so the deadline hasn't passed for the guest yet.

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-07 Thread Nadav Amit
Thanks for reviewing this patch and the rest of the gang. On Oct 6, 2014, at 11:57 PM, Radim Krčmář rkrc...@redhat.com wrote: 2014-10-03 01:10+0300, Nadav Amit: Setting the TSC deadline MSR that are initiated by the host (using ioctl's) may cause superfluous interrupt. This occurs in the

Re: [PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-06 Thread Radim Krčmář
2014-10-03 01:10+0300, Nadav Amit: Setting the TSC deadline MSR that are initiated by the host (using ioctl's) may cause superfluous interrupt. This occurs in the following case: 1. A TSC deadline timer interrupt is pending. 2. TSC deadline was still not cleared (which happens during

[PATCH 5/5] KVM: x86: Using TSC deadline may cause multiple interrupts by user writes

2014-10-02 Thread Nadav Amit
Setting the TSC deadline MSR that are initiated by the host (using ioctl's) may cause superfluous interrupt. This occurs in the following case: 1. A TSC deadline timer interrupt is pending. 2. TSC deadline was still not cleared (which happens during vcpu_run). 3. Userspace uses