On Fri, Sep 26, 2014 at 09:51:15AM +0200, Christoffer Dall wrote:
On Tue, Sep 16, 2014 at 08:57:31AM -0400, Andrew Jones wrote:
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches
On Tue, Sep 16, 2014 at 08:57:31AM -0400, Andrew Jones wrote:
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't require any synchronization.
So we
Il 16/09/2014 04:06, Andrew Jones ha scritto:
We shouldn't try Load-Exclusive instructions unless we've enabled memory
management, as these instructions depend on the data cache unit's
coherency monitor. This patch adds a new setup boolean, initialized to false,
that is used to guard
Il 16/09/2014 04:06, Andrew Jones ha scritto:
We shouldn't try Load-Exclusive instructions unless we've enabled memory
management, as these instructions depend on the data cache unit's
coherency monitor. This patch adds a new setup boolean, initialized to false,
that is used to guard
- Original Message -
Il 16/09/2014 04:06, Andrew Jones ha scritto:
We shouldn't try Load-Exclusive instructions unless we've enabled memory
management, as these instructions depend on the data cache unit's
coherency monitor. This patch adds a new setup boolean, initialized to
Il 16/09/2014 14:12, Andrew Jones ha scritto:
Should it at least write 1 to the spinlock?
I thought about that. So on one hand we might get a somewhat functional
synchronization mechanism, which may be enough for some unit test that
doesn't enable caches, but still needs it. On the other
- Original Message -
Il 16/09/2014 14:12, Andrew Jones ha scritto:
Should it at least write 1 to the spinlock?
I thought about that. So on one hand we might get a somewhat functional
synchronization mechanism, which may be enough for some unit test that
doesn't enable caches,
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't require any synchronization.
So we should be able to do
enable caches
spin_lock
start other processors
spin_unlock
Ok,
- Original Message -
- Original Message -
Il 16/09/2014 14:12, Andrew Jones ha scritto:
Should it at least write 1 to the spinlock?
I thought about that. So on one hand we might get a somewhat functional
synchronization mechanism, which may be enough for some
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't require any synchronization.
So we should be able to do
enable caches
spin_lock
start
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't require any synchronization.
So we should be able to do
enable caches
spin_lock
start
- Original Message -
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't require any synchronization.
So we should be able to do
On Tue, Sep 16, 2014 at 10:38:11AM -0400, Andrew Jones wrote:
- Original Message -
- Original Message -
Il 16/09/2014 14:43, Andrew Jones ha scritto:
I don't think we need to worry about this case. AFAIU, enabling the
caches for a particular cpu shouldn't
We shouldn't try Load-Exclusive instructions unless we've enabled memory
management, as these instructions depend on the data cache unit's
coherency monitor. This patch adds a new setup boolean, initialized to false,
that is used to guard Load-Exclusive instructions. Eventually we'll add more
14 matches
Mail list logo
