Hi Christoffer,
On 15/10/14 17:25, Christoffer Dall wrote:
On Thu, Aug 21, 2014 at 02:06:42PM +0100, Andre Przywara wrote:
The virtual MPIDR registers (containing topology information) for the
guest are currently mapped linearily to the vcpu_id. Improve this
mapping for arm64 by using three
On Thu, Aug 21, 2014 at 02:06:42PM +0100, Andre Przywara wrote:
The virtual MPIDR registers (containing topology information) for the
guest are currently mapped linearily to the vcpu_id. Improve this
mapping for arm64 by using three levels to not artificially limit the
number of vCPUs. Also
The virtual MPIDR registers (containing topology information) for the
guest are currently mapped linearily to the vcpu_id. Improve this
mapping for arm64 by using three levels to not artificially limit the
number of vCPUs. Also add an accessor to later allow easier access to
a vCPU with a given
