[PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs

2015-09-29 Thread Christoffer Dall
The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the re

Re: [PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs

2015-10-02 Thread Andre Przywara
Hi Christoffer, On 29/09/15 15:49, Christoffer Dall wrote: > The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. > We currently simulate this behavior by writing a hardcoded value to the > register for the SGIs and PPIs on every write of these bits to the > register (ignoring wha

Re: [PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs

2015-10-02 Thread Christoffer Dall
On Fri, Oct 02, 2015 at 03:51:50PM +0100, Andre Przywara wrote: > Hi Christoffer, > > On 29/09/15 15:49, Christoffer Dall wrote: > > The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. > > We currently simulate this behavior by writing a hardcoded value to the > > register for th