From: Yang Zhang
basically to benefit from apicv, we need clear MSR bitmap for
corresponding x2apic MSRs when guest enabled x2apic:
0x800 - 0x8ff: no read intercept for apicv register virtualization
TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery
Signed-off-by: Yang Z
On Mon, Jan 07, 2013 at 10:02:37AM +0800, Yang Zhang wrote:
> From: Yang Zhang
>
> basically to benefit from apicv, we need clear MSR bitmap for
> corresponding x2apic MSRs when guest enabled x2apic:
> 0x800 - 0x8ff: no read intercept for apicv register virtualization
> TPR,EOI,SELF-IPI:
Gleb Natapov wrote on 2013-01-07:
> On Mon, Jan 07, 2013 at 10:02:37AM +0800, Yang Zhang wrote:
>> From: Yang Zhang
>>
>> basically to benefit from apicv, we need clear MSR bitmap for
>> corresponding x2apic MSRs when guest enabled x2apic:
>> 0x800 - 0x8ff: no read intercept for apicv registe
On Mon, Jan 07, 2013 at 06:58:15AM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-07:
> > On Mon, Jan 07, 2013 at 10:02:37AM +0800, Yang Zhang wrote:
> >> From: Yang Zhang
> >>
> >> basically to benefit from apicv, we need clear MSR bitmap for
> >> corresponding x2apic MSRs when gues