On 10/24/2012 11:19 AM, Stefan Fritsch wrote:
With the decode table fix I think it should work.
It needs some more changes. The patch below did the trick for me. It is
against 3.5, because I didn't want to build a whole new kernel (my test
machine is a dead slow AMD E-350).
The patch is
On 10/20/2012 12:39 AM, Stefan Fritsch wrote:
On Thursday 18 October 2012, Avi Kivity wrote:
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
You misunderstood the description. V_INTR_MASKING=1 means that
CR8 writes are not propagated to real HW APIC.
But KVM does not trap access to CR8
On Thursday 18 October 2012, Avi Kivity wrote:
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
You misunderstood the description. V_INTR_MASKING=1 means that
CR8 writes are not propagated to real HW APIC.
But KVM does not trap access to CR8 unconditionally. It enables
CR8 intercept only
On 2012-10-17 21:24, Stefan Fritsch wrote:
Hi,
OpenBSD/i386 seems to be one of the few operating systems that still
uses the LAPIC taks priority register for interrupt handling. On AMD
Yeah, only very special OSes do this... ;)
CPUs and on older Intel CPUs without the flexpriority
Hi Jan,
On Thu, 18 Oct 2012, Jan Kiszka wrote:
There is also the kvmvapic, but kvm does not expose a sane interface
to it and only uses it for Windows XP specific binary patching.
The kvmvapic is not a classic paravirtual interface in that it does not
really require guest OS awareness. But it
On Thu, Oct 18, 2012 at 09:43:46AM +0200, Stefan Fritsch wrote:
Everything that unconditionally traps, and so do CR8 accesses, does not
help.
I was hoping that CR8 access would not trap unconditionally. The AMD
Programmer's Manual Vol. 2, section 15.21.2 seems to imply that
there is a mode
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes
are not propagated to real HW APIC.
But KVM does not trap access to CR8 unconditionally. It enables CR8
intercept only when there is pending interrupt in IRR that cannot be
On Thu, 18 Oct 2012, Avi Kivity wrote:
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes
are not propagated to real HW APIC.
But KVM does not trap access to CR8 unconditionally. It enables CR8
intercept only when there is
Hi,
OpenBSD/i386 seems to be one of the few operating systems that still
uses the LAPIC taks priority register for interrupt handling. On AMD
CPUs and on older Intel CPUs without the flexpriority feature, this
causes a huge performance impact on kvm. I have seen slowdown by a
factor of 10.
