On 01/22/2014 12:22 PM, Peter Maydell wrote:
On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat
On 01/28/2014 01:27 AM, Benjamin Herrenschmidt wrote:
On Wed, 2014-01-22 at 17:29 +, Peter Maydell wrote:
Basically if it would be on real bus, get byte value
that corresponds to phys_addr + 0 address place
it into data[0], get byte value that corresponds to
phys_addr + 1 address place it
On Tue, Jan 28, 2014 at 03:47:32PM +1100, Benjamin Herrenschmidt wrote:
On Mon, 2014-01-27 at 16:44 -0800, Christoffer Dall wrote:
I'm loosing track of this discussion, Ben, can you explain a bit? You
wrote:
Having a byte array coming in that represents what the CPU does in its
On Wed, 2014-01-22 at 17:29 +, Peter Maydell wrote:
Basically if it would be on real bus, get byte value
that corresponds to phys_addr + 0 address place
it into data[0], get byte value that corresponds to
phys_addr + 1 address place it into data[1], etc.
This just isn't how real
On Wed, 2014-01-22 at 11:29 -0800, Victor Kamensky wrote:
I don't see why you so attached to desire to describe
data part of memory transaction as just one of int
types. If we are talking about bunch of hypothetical
cases imagine such bus that allow transaction with
size of 6 bytes. How do
On Wed, 2014-01-22 at 20:02 +, Peter Maydell wrote:
Defining it as being always guest-order would mean that
userspace had to continually look at the guest CPU
endianness bit, which is annoying and awkward.
Defining it as always host-endian order is the most
reasonable option
On 27 January 2014 23:34, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Wed, 2014-01-22 at 20:02 +, Peter Maydell wrote:
Defining it as being always guest-order would mean that
userspace had to continually look at the guest CPU
endianness bit, which is annoying and awkward.
On Tue, 2014-01-28 at 11:07 +1100, Benjamin Herrenschmidt wrote:
On Thu, 2014-01-23 at 15:33 +, Peter Maydell wrote:
(4) PPC CPUs in BE mode and ARM CPUs in BE mode are not
the same, because in the ARM case it is doing an
internal-to-CPU byteswap, and in the PPC case it is
On Thu, 2014-01-23 at 15:33 +, Peter Maydell wrote:
(4) PPC CPUs in BE mode and ARM CPUs in BE mode are not
the same, because in the ARM case it is doing an
internal-to-CPU byteswap, and in the PPC case it is not
Aren't they both byte-order invariant ?
In that case they are the
The point is simple, and Peter has made it over and over:
Any consumer of a memory operation sees value, len, address.
This is what KVM_EXIT_MMIO emulates. So just by knowing the ABI
definition and having a pointer to the structure you need to be able to
tell me value, len, address.
But
On Thu, 2014-01-23 at 20:11 -0800, Victor Kamensky wrote:
I would take 50 byteswaps with a clear ABI any day over an obscure
standard that can avoid a single hardware-on-register instruction.
This
is about designing a clean software interface, not about building an
optimized integrated
On Mon, 2014-01-27 at 23:49 +, Peter Maydell wrote:
Er, what? If we make the array be guest's current order
then by definition userspace has to look at the guest's
current endianness. I agree that would be bad. Either
of the two current proposals (host kernel order; guest
CPU's
On Tue, Jan 28, 2014 at 11:32:41AM +1100, Benjamin Herrenschmidt wrote:
On Thu, 2014-01-23 at 20:11 -0800, Victor Kamensky wrote:
I would take 50 byteswaps with a clear ABI any day over an obscure
standard that can avoid a single hardware-on-register instruction.
This
is about
On Tue, Jan 28, 2014 at 11:36:13AM +1100, Benjamin Herrenschmidt wrote:
On Mon, 2014-01-27 at 23:49 +, Peter Maydell wrote:
Er, what? If we make the array be guest's current order
then by definition userspace has to look at the guest's
current endianness. I agree that would be bad.
On Mon, 2014-01-27 at 16:44 -0800, Christoffer Dall wrote:
I'm loosing track of this discussion, Ben, can you explain a bit? You
wrote:
Having a byte array coming in that represents what the CPU does in its
current byte order means you do *NOT* need to query the endianness of
the
On 23 January 2014 00:22, Victor Kamensky victor.kamen...@linaro.org wrote:
Peter, could I please ask you a favor. Could you please
stop deleting pieces of your and my previous responses
when you reply.
No, sorry. It produces excessively long and totally unreadable
emails for everybody else if
On 23.01.2014, at 05:25, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Alex,
Sorry, for delayed reply, I was focusing on discussion
with Peter. Hope you and other folks may get something
out of it :).
Please see responses inline
On 22 January 2014 02:52, Alexander Graf
On Wed, 22 Jan 2014 20:25:05 -0800
Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Alex,
Sorry, for delayed reply, I was focusing on discussion
with Peter. Hope you and other folks may get something
out of it :).
Please see responses inline
On 22 January 2014 02:52, Alexander
On 23 January 2014 02:23, Peter Maydell peter.mayd...@linaro.org wrote:
On 23 January 2014 00:22, Victor Kamensky victor.kamen...@linaro.org wrote:
Peter, could I please ask you a favor. Could you please
stop deleting pieces of your and my previous responses
when you reply.
No, sorry. It
On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote:
In [1] I wrote
I don't see why you so attached to desire to describe
data part of memory transaction as just one of int
types. If we are talking about bunch of hypothetical
cases imagine such bus that allow
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote:
On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote:
In [1] I wrote
I don't see why you so attached to desire to describe
data part of memory transaction as just one of int
types. If we are talking
On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote:
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote:
On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org
wrote:
In [1] I wrote
I don't see why you so attached to desire to describe
On Wed, Jan 22, 2014 at 02:27:29PM +0530, Anup Patel wrote:
[...]
Thanks for the info on QEMU side handling of MMIO data.
I was not aware that we would be only have target endian = LE
for ARM/ARM64 in QEMU. I think Marc Z had mentioned similar
thing about MMIO this in our previous
On 23 January 2014 08:25, Victor Kamensky victor.kamen...@linaro.org wrote:
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote:
On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org wrote:
In [1] I wrote
I don't see why you so attached to desire to describe
On 23 January 2014 12:45, Christoffer Dall christoffer.d...@linaro.org wrote:
On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote:
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote:
On 23 January 2014 15:06, Victor Kamensky victor.kamen...@linaro.org
wrote:
On Thu, Jan 23, 2014 at 04:50:18PM -0800, Victor Kamensky wrote:
On 23 January 2014 12:45, Christoffer Dall christoffer.d...@linaro.org
wrote:
On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote:
On 23 January 2014 07:33, Peter Maydell peter.mayd...@linaro.org wrote:
On 23
On 23 January 2014 18:14, Christoffer Dall christoffer.d...@linaro.org wrote:
On Thu, Jan 23, 2014 at 04:50:18PM -0800, Victor Kamensky wrote:
On 23 January 2014 12:45, Christoffer Dall christoffer.d...@linaro.org
wrote:
On Thu, Jan 23, 2014 at 08:25:35AM -0800, Victor Kamensky wrote:
On
Hi Alex,
On Wed, Jan 22, 2014 at 12:11 PM, Alexander Graf ag...@suse.de wrote:
Am 22.01.2014 um 07:31 schrieb Anup Patel a...@brainfault.org:
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat and Christoffer asked me to follow
up on
On 22.01.2014, at 08:26, Victor Kamensky victor.kamen...@linaro.org wrote:
On 21 January 2014 22:41, Alexander Graf ag...@suse.de wrote:
Native endian really is just a shortcut for target endian
which is LE for ARM and BE for PPC. There shouldn't be
a qemu-system-armeb or
Hi Peter,
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not
On 22 January 2014 17:19, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
but the major issue here is that the data being
transferred is not just a bag of bytes. The data[]
array plus the size field are being (mis)used
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 17:19, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
but the major issue here is that the data being
transferred is not just a
On 22 January 2014 19:29, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
This just isn't how real buses work. There is no
address + 1, address + 2. There is a single address
for the memory transaction and a set of data
On 22 January 2014 12:02, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 19:29, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
This just isn't how real buses work. There is no
address + 1, address + 2.
On 22 January 2014 22:47, Victor Kamensky victor.kamen...@linaro.org wrote:
You deleted my example, but I need it again:
Consider the following ARM code snippets:
setend le
mov r1, #0x04030201
str r1, [r0]
and
setend be
mov r1, #0x01020304
str r1, [r0]
Just for LE host case basically
Peter, could I please ask you a favor. Could you please
stop deleting pieces of your and my previous responses
when you reply.
Please just reply inline. Sometimes I would like to
reference my or your previous statement, but I could not
find it in your response email. It is very bizzar. Sorry,
it
Hi Alex,
Sorry, for delayed reply, I was focusing on discussion
with Peter. Hope you and other folks may get something
out of it :).
Please see responses inline
On 22 January 2014 02:52, Alexander Graf ag...@suse.de wrote:
On 22.01.2014, at 08:26, Victor Kamensky victor.kamen...@linaro.org
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat and Christoffer asked me to follow
up on this thread.
Here it goes. Sorry, it is very long email.
I don't believe we can
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat and Christoffer asked me to follow
Am 22.01.2014 um 07:31 schrieb Anup Patel a...@brainfault.org:
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not
On 21 January 2014 22:41, Alexander Graf ag...@suse.de wrote:
Am 22.01.2014 um 07:31 schrieb Anup Patel a...@brainfault.org:
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night.
On 18.01.2014, at 11:15, Peter Maydell peter.mayd...@linaro.org wrote:
On 18 January 2014 07:32, Alexander Graf ag...@suse.de wrote:
Am 18.01.2014 um 05:24 schrieb Christoffer Dall
christoffer.d...@linaro.org:
On Fri, Jan 17, 2014 at 06:52:57PM +, Peter Maydell wrote:
Having thought a
On 17.01.2014, at 19:52, Peter Maydell peter.mayd...@linaro.org wrote:
On 17 January 2014 17:53, Peter Maydell peter.mayd...@linaro.org wrote:
Specifically, the KVM API says here's a uint8_t[] byte
array and a length, and the current QEMU code treats that
as this is a byte array written as
On 20 January 2014 14:20, Alexander Graf ag...@suse.de wrote:
I think I see the problem now. You're thinking about LE hosts, not LE guests.
I think the only really sensible options would be to
a) Always use a statically define target endianness (big for ppc)
b) Always use host endianness
On Mon, Jan 20, 2014 at 03:22:11PM +0100, Alexander Graf wrote:
On 17.01.2014, at 19:52, Peter Maydell peter.mayd...@linaro.org wrote:
On 17 January 2014 17:53, Peter Maydell peter.mayd...@linaro.org wrote:
Specifically, the KVM API says here's a uint8_t[] byte
array and a length, and
On 18 January 2014 07:32, Alexander Graf ag...@suse.de wrote:
Am 18.01.2014 um 05:24 schrieb Christoffer Dall
christoffer.d...@linaro.org:
On Fri, Jan 17, 2014 at 06:52:57PM +, Peter Maydell wrote:
Having thought a little more about this, my opinion is:
* we should specify that the byte
[This seemed like a good jumping off point for this question.]
On 16 January 2014 17:51, Alexander Graf ag...@suse.de wrote:
Am 16.01.2014 um 18:41 schrieb Peter Maydell peter.mayd...@linaro.org:
Also see my remarks on the previous patch series suggesting
that we should look at this in a more
On 17 January 2014 17:53, Peter Maydell peter.mayd...@linaro.org wrote:
Specifically, the KVM API says here's a uint8_t[] byte
array and a length, and the current QEMU code treats that
as this is a byte array written as if the guest CPU
(a) were in TARGET_WORDS_BIGENDIAN order and (b) wrote
On Fri, Jan 17, 2014 at 06:52:57PM +, Peter Maydell wrote:
On 17 January 2014 17:53, Peter Maydell peter.mayd...@linaro.org wrote:
Specifically, the KVM API says here's a uint8_t[] byte
array and a length, and the current QEMU code treats that
as this is a byte array written as if the
Am 18.01.2014 um 05:24 schrieb Christoffer Dall christoffer.d...@linaro.org:
On Fri, Jan 17, 2014 at 06:52:57PM +, Peter Maydell wrote:
On 17 January 2014 17:53, Peter Maydell peter.mayd...@linaro.org wrote:
Specifically, the KVM API says here's a uint8_t[] byte
array and a length,
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