/me reminds you of 78 char text wrap.
On Wed, Jul 09, 2014 at 07:32:09PM +, Liang, Kan wrote:
> > Sure; but what I meant was, check_msr() is broken when ran on such a
> > kernel. You need to fix check_msr() to return failure on these 'ignored'
> > MSRs, after all they don't function as expecte
> > >
> > > On Wed, Jul 09, 2014 at 02:32:28PM +, Liang, Kan wrote:
> > > >
> > > >
> > > > > On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> > > > > > +/*
> > > > > > + * Under certain circumstances, access certain MSR may cause #GP.
> > > > > > + * The function tests
vger.kernel.org; kvm@vger.kernel.org
> > Subject: Re: [PATCH V4 1/2] perf ignore LBR and extra_regs.
> >
> > On Wed, Jul 09, 2014 at 02:32:28PM +, Liang, Kan wrote:
> > >
> > >
> > > > On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wr
> -Original Message-
> From: Peter Zijlstra [mailto:pet...@infradead.org]
> Sent: Wednesday, July 09, 2014 10:58 AM
> To: Liang, Kan
> Cc: a...@firstfloor.org; linux-ker...@vger.kernel.org; kvm@vger.kernel.org
> Subject: Re: [PATCH V4 1/2] perf ignore LBR and extra_regs
On Wed, Jul 09, 2014 at 02:32:28PM +, Liang, Kan wrote:
>
>
> > On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> > > +/*
> > > + * Under certain circumstances, access certain MSR may cause #GP.
> > > + * The function tests if the input MSR can be safely accessed.
> > > +
> On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> > +/*
> > + * Under certain circumstances, access certain MSR may cause #GP.
> > + * The function tests if the input MSR can be safely accessed.
> > + */
> > +static inline bool check_msr(unsigned long msr) {
> > + u64 val
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> +/*
> + * Under certain circumstances, access certain MSR may cause #GP.
> + * The function tests if the input MSR can be safely accessed.
> + */
> +static inline bool check_msr(unsigned long msr)
> +{
> + u64 value;
> +
> +
>
> On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> > --- a/arch/x86/kernel/cpu/perf_event.h
> > +++ b/arch/x86/kernel/cpu/perf_event.h
> > @@ -464,6 +464,12 @@ struct x86_pmu {
> > */
> > struct extra_reg *extra_regs;
> > unsigned int er_flags;
> > + /*
> >
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> --- a/arch/x86/kernel/cpu/perf_event.h
> +++ b/arch/x86/kernel/cpu/perf_event.h
> @@ -464,6 +464,12 @@ struct x86_pmu {
>*/
> struct extra_reg *extra_regs;
> unsigned int er_flags;
> + /*
> + * EXTRA
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> + /*
> + * Access LBR MSR may cause #GP under certain circumstances.
> + * E.g. KVM doesn't support LBR MSR
> + * Check all LBT MSR here.
> + * Disable LBR access if any LBR MSRs can not be accessed.
> +
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> diff --git a/arch/x86/kernel/cpu/perf_event.c
> b/arch/x86/kernel/cpu/perf_event.c
> index 2bdfbff..f0e8022 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -118,6 +118,9 @@ static i
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.li...@intel.com wrote:
> diff --git a/arch/x86/kernel/cpu/perf_event.c
> b/arch/x86/kernel/cpu/perf_event.c
> index 2bdfbff..f0e8022 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -118,6 +118,9 @@ static i
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