Il 05/09/2013 11:24, Zhang, Yang Z ha scritto:
Here I have such consideration: this logic is wrong if CPU support
PIN_BASED_VMX_PREEMPTION_TIMER but doesn't support
VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, though I don't know if this does
occurs. So the codes above reads the MSR and reserves the
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2-L0 with some
reasons not emulated by L1, preemption timer value should be save in such
exits.
2. Add support of Save VMX-preemption timer value
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2-L0 with some
reasons not emulated by L1, preemption timer value
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2-L0
with some reasons not
On Thu, Sep 5, 2013 at 5:24 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug
Arthur Chunqi Li wrote on 2013-09-05:
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch contains the following two changes:
1. Fix the bug in nested preemption timer
On Thu, Sep 5, 2013 at 7:05 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
Arthur Chunqi Li wrote on 2013-09-05:
Arthur Chunqi Li wrote on 2013-09-05:
On Thu, Sep 5, 2013 at 3:45 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
Arthur Chunqi Li wrote on 2013-09-04:
This patch
