Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
@@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
(unsigned long
*)__get_free_page(GFP_KERNEL);
if
On Wed, Jan 28, 2015 at 9:06 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
__clear_bit(msr, msr_bitmap_nested + 0x000 / f);
Anyway, this is not necessary for your current patch. We can consider
it later if there really have other features will use it.
Yep, I know what you mean
On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should only be loaded in non-nested entry.
Currently we only clear the
Zhang, Yang Z wrote on 2015-01-28:
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should only
Wincy Van wrote on 2015-01-24:
Currently, if L1 enables MSR_BITMAP, we will emulate this feature, all of L2's
msr access is intercepted by L0. Since many features like virtualize x2apic
mode
has a complicated logic and it is difficult for us to emulate, we should use
hardware and merge the
Zhang, Yang Z wrote on 2015-01-28:
Wincy Van wrote on 2015-01-24:
When L2 is using x2apic, we can use virtualize x2apic mode to gain
higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls for the
nested apicv patches.
Sorry, replied on the
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should only be loaded in non-nested entry.
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
You are right, but this is not fit for all the cases, we should
custom the nested_msr_bitmap.
e.g. Currently L0 wants to intercept some of the x2apic msrs' reading:
if
Wincy Van wrote on 2015-01-24:
When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls for the nested
apicv patches.
Signed-off-by: Wincy Van fanwenyi0...@gmail.com
---
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z yang.z.zh...@intel.com
wrote:
Wincy Van wrote on 2015-01-28:
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
yang.z.zh...@intel.com
wrote:
@@ -8344,7 +8394,68 @@ static int
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
You are right, but this is not fit for all the cases, we should
custom the nested_msr_bitmap.
e.g. Currently L0 wants to intercept some of the x2apic msrs' reading:
if (enable_apicv) {
for
On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z yang.z.zh...@intel.com wrote:
@@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
(unsigned long
*)__get_free_page(GFP_KERNEL);
if (!vmx_msr_bitmap_longmode_x2apic)
goto out4;
+
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