: Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for
bolted TLB miss crit int
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for
guests.
Avoid SPRG4-7 usage as scratch in host exception handlers
: Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for
bolted TLB miss crit int
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for
guests.
Avoid SPRG4-7 usage as scratch in host exception handlers
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is
On 06/25/2012 07:26 AM, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is
On 06/25/2012 07:26 AM, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the
