Hi there, When I test nested EPT (enable EPT of L2->L1 address translation), it occurred some questions when query IA32_VMX_EPT_VPID_CAP.
1. It show that bit 16 and 17 (support for 1G and 2M page) are disabled in nested IA32_VMX_EPT_VPID_CAP. Why nested EPT fails to support these? Are there any difficulties? 2. Can the bit 6 (support for a page-walk length of 4) of IA32_VMX_EPT_VPID_CAP is 0? That is to say if I can design a paging structure >4 or <4 levels? Cause I don't know who is the original author of nested EPT, I send this mail to the whole list. If anyone knows please tell me and CC the authors for more detailed discussion. Thanks, Arthur -- Arthur Chunqi Li Department of Computer Science School of EECS Peking University Beijing, China -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
