Re: [PATCH v4 0/8] arm/arm64: KVM: dynamic VGIC sizing

Hi all, I have a problem that I want to ask for your advice. Before I send this mail to Marc and Christoffer. But it seems that they are busy or not online recently. I git clone Marc's kvmtool-vgic-dyn branch and run it on Fastmodel Cortex-A57*4 with qemu 2.1.0.

Re: [PATCH v4 0/8] arm/arm64: KVM: dynamic VGIC sizing

On 2014/9/25 21:35, Christoffer Dall wrote: On Thu, Sep 25, 2014 at 08:44:16PM +0800, Shannon Zhao wrote: Hi all, I have a problem that I want to ask for your advice. Before I send this mail to Marc and Christoffer. But it seems that they are busy or not online recently. I git clone

Re: [PATCH] arm/arm64: KVM: Fix set_clear_sgi_pend_reg offset

. This showed up as bugs in kfree() and the kernel complaining a lot of you turn on memory debugging. This addresses: http://marc.info/?l=kvmm=141164910007868w=2 Reported-by: Shannon Zhao zhaoshengl...@huawei.com Signed-off-by: Christoffer Dall christoffer.d...@linaro.org --- virt/kvm

Re: [PATCH] arm/arm64: KVM: Fix set_clear_sgi_pend_reg offset

On 2014/9/26 16:44, Christoffer Dall wrote: Hi Shannon, On Fri, Sep 26, 2014 at 01:57:46PM +0800, Shannon Zhao wrote: On 2014/9/26 1:49, Christoffer Dall wrote: The sgi values calculated in read_set_clear_sgi_pend_reg() and write_set_clear_sgi_pend_reg() were horribly incorrectly

Re: [PATCH] arm/arm64: KVM: Fix set_clear_sgi_pend_reg offset

. This showed up as bugs in kfree() and the kernel complaining a lot of you turn on memory debugging. This addresses: http://marc.info/?l=kvmm=141164910007868w=2 Reported-by: Shannon Zhao zhaoshengl...@huawei.com Signed-off-by: Christoffer Dall christoffer.d...@linaro.org --- virt/kvm

Re: [PATCH] arm/arm64: KVM: Fix set_clear_sgi_pend_reg offset

Hi Christoffer, On 2014/9/26 21:44, Christoffer Dall wrote: On Fri, Sep 26, 2014 at 12:16:35PM +0200, Christoffer Dall wrote: On Fri, Sep 26, 2014 at 05:26:00PM +0800, Shannon Zhao wrote: On 2014/9/26 16:44, Christoffer Dall wrote: Hi Shannon, On Fri, Sep 26, 2014 at 01:57:46PM +0800

Re: The status about vhost-net on kvm-arm?

Hi Nikolay, From this mail I know you guys have done some work about ioeventfd support on kvm-arm before. Do you have plan to rework your patch based on the new branch? If not, I think we should send a patch to make eventfd support on kvm-arm and make vhost-net work. Based on the new kvm-arm

Re: [RFC PATCH 3/5] KVM: ARM VGIC add kvm_io_bus_ frontend

On 2014/11/25 5:26, Nikolay Nikolaev wrote: In io_mem_abort remove the call to vgic_handle_mmio. The target is to have a single MMIO handling path - that is through the kvm_io_bus_ API. Register a kvm_io_device in kvm_vgic_init on the whole vGIC MMIO region. Both read and write calls are

Re: [RFC PATCH 4/5] ARM: enable linking against eventfd and irqchip

On 2014/11/25 5:27, Nikolay Nikolaev wrote: This enables compilation of the eventfd feature on ARM. Only enable on ARM? I think we should enable it on ARM64 as well because the eventfd featrue is common for ARM32 and ARM64. Thanks, Shannon Signed-off-by: Nikolay Nikolaev

[PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao shannon.z...@linaro.org We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/include/asm

[PATCH 02/18] KVM: ARM64: Add initial support for PMU

From: Shannon Zhao shannon.z...@linaro.org Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit

[PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao shannon.z...@linaro.org To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel anup.pa...@linaro.org Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/include/asm

[PATCH 00/18] KVM: ARM64: Add guest PMU support

From: Shannon Zhao shannon.z...@linaro.org This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get

[PATCH 06/18] KVM: ARM64: Add reset and access handlers for PMCEID0_EL0 and PMCEID1_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Add reset handler which gets host value of PMCEID0_EL0 or PMCEID1_EL0. Add access handler which emulates writing and reading PMCEID0_EL0 or PMCEID1_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c | 36

[PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add access handler which emulates writing and reading PMCR_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm

[PATCH 17/18] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao shannon.z...@linaro.org When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, if vcpu doesn't run, call irq_work_queue to wake up vcpu. Otherwise call kvm_vgic_inject_irq to inject the interrupt. Signed

[PATCH 12/18] KVM: ARM64: Add reset and access handlers for PMINTENSET_EL1 and PMINTENCLR_EL1 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMINTENSET_EL1 and PMINTENCLR_EL1 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMINTENSET_EL1 or PMINTENCLR_EL1 register. When writing to PMINTENSET_EL1, set

[PATCH 07/18] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao shannon.z...@linaro.org When we use tools like perf on host, perf passes the event type and the id in this type category to kernel, then kernel will map them to event number and write this number to PMU PMEVTYPERn_EL0 register. While we're trapping and emulating guest accesses

[PATCH 15/18] KVM: ARM64: Add reset and access handlers for PMSWINC_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Add access handler which emulates writing and reading PMSWINC_EL0 register and add support for creating software increment event. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c | 15 ++- include/kvm

[PATCH 13/18] KVM: ARM64: Add reset and access handlers for PMOVSSET_EL0 and PMOVSCLR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMOVSSET_EL0 and PMOVSCLR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMOVSSET_EL0 or PMOVSCLR_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org

[PATCH 14/18] KVM: ARM64: Add reset and access handlers for PMUSERENR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMUSERENR_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c

[PATCH 10/18] KVM: ARM64: Add reset and access handlers for PMCCNTR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMCCNTR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMCCNTR_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c | 19

[PATCH 08/18] KVM: ARM64: Add reset and access handlers for PMXEVTYPER_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When writing to PMXEVTYPER_EL0, call kvm_pmu_set_counter_event_type create a perf

[PATCH 18/18] KVM: ARM64: Add KVM_CAP_ARM_PMU and KVM_ARM_PMU_SET_IRQ

From: Shannon Zhao shannon.z...@linaro.org Add KVM_CAP_ARM_PMU for userspace to check whether KVM supports PMU. Add KVM_ARM_PMU_SET_IRQ for userspace to set PMU IRQ number. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm/kvm/arm.c | 8 include/kvm/arm_pmu.h

[PATCH 16/18] KVM: ARM64: Add access handlers for PMEVCNTRn_EL0 and PMEVTYPERn_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Add access handler which emulates writing and reading PMEVCNTRn_EL0 and PMEVTYPERn_EL0. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c | 106 ++ 1 file changed, 106

[PATCH 09/18] KVM: ARM64: Add reset and access handlers for PMXEVCNTR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMXEVTYPER_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER_EL0 register. When reading PMXEVCNTR_EL0, call perf_event_read_value to get the count value

[PATCH 05/18] KVM: ARM64: Add reset and access handlers for PMSELR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMSELR_EL0 register. Signed-off-by: Shannon Zhao shannon.z...@linaro.org --- arch/arm64/kvm/sys_regs.c | 26

[PATCH 11/18] KVM: ARM64: Add reset and access handlers for PMCNTENSET_EL0 and PMCNTENCLR_EL0 register

From: Shannon Zhao shannon.z...@linaro.org Since the reset value of PMCNTENSET_EL0 and PMCNTENCLR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMCNTENSET_EL0 or PMCNTENCLR_EL0 register. When writing to PMCNTENSET_EL0, call

Re: [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

On 2015/7/17 18:17, Christoffer Dall wrote: On Fri, Jul 17, 2015 at 04:25:06PM +0800, Shannon Zhao wrote: On 2015/7/17 2:45, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:33AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org We are about to trap

Re: [PATCH 02/18] KVM: ARM64: Add initial support for PMU

On 2015/7/17 17:58, Christoffer Dall wrote: On Fri, Jul 17, 2015 at 04:13:35PM +0800, Shannon Zhao wrote: On 2015/7/17 2:25, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:32AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org Here we plan to support

Re: [PATCH 02/18] KVM: ARM64: Add initial support for PMU

On 2015/7/17 2:25, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:32AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing

Re: [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/7/17 3:55, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add access handler which

Re: [PATCH 03/18] KVM: ARM64: Add offset defines for PMU registers

On 2015/7/17 2:45, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:33AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU

Re: [PATCH 07/18] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/7/17 22:30, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:37AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org When we use tools like perf on host, perf passes the event type and the id in this type category to kernel, then kernel will map

Re: [PATCH 04/18] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/7/17 18:21, Christoffer Dall wrote: On Fri, Jul 17, 2015 at 04:45:44PM +0800, Shannon Zhao wrote: On 2015/7/17 3:55, Christoffer Dall wrote: On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org Add reset handler which

Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support

On 2015/10/26 19:33, Christoffer Dall wrote: > On Thu, Sep 24, 2015 at 03:31:05PM -0700, Shannon Zhao wrote: >> This patchset adds guest PMU support for KVM on ARM64. It takes >> trap-and-emulate approach. When guest wants to monitor one event, it >> will be trapped by

[PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao <shannon.z...@linaro.org> When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao <shannon.z...@l

[PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, pend PMU interrupt. When the value w

[PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao <shannon.z...@linaro.org> According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When wri

[PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao <shannon.z...@linaro.org> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/ua

[PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao <shannon.z...@linaro.org> Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E to zero. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Sign

[PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> ---

[PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao <shannon.z...@linaro.org> When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files

[PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao <shannon.z...@linaro.org> When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 19 ++

[PATCH v4 00/21] KVM: ARM64: Add guest PMU support

From: Shannon Zhao <shannon.z...@linaro.org> This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs

[PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register

From: Shannon Zhao <shannon.z...@linaro.org> The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shanno

[PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao <shannon.z...@linaro.org> Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monito

[PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao <shannon.z...@linaro.org> We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64

[PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf

[PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register

From: Shannon Zhao <shannon.z...@linaro.org> Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 18 +++-

[PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- ar

[PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao <shannon.z...@linaro.org> When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event

[PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of th

[PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

From: Shannon Zhao <shannon.z...@linaro.org> Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 16

[PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

From: Shannon Zhao <shannon.z...@linaro.org> Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys

[PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_even

[PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Add a helper fo

[PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading and writing to PMCCNTR register. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys

Re: [Qemu-devel] [PATCH v7 03/35] acpi: add aml_create_field

On 2015/11/2 17:13, Xiao Guangrong wrote: > Implement CreateField term which is used by NVDIMM _DSM method in later patch > > Signed-off-by: Xiao Guangrong > --- > hw/acpi/aml-build.c | 13 + > include/hw/acpi/aml-build.h | 1 + > 2 files

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

iate base, > please suggest rules for selecting the more suitable base] > > url: > https://github.com/0day-ci/linux/commits/Shannon-Zhao/KVM-ARM64-Add-guest-PMU-support/20151030-143148 > config: arm-axm55xx_defconfig (attached as .config) > reproduce: > wget >

Re: [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

On 2015/11/3 4:54, Christopher Covington wrote: > Hi Shannon, > > On 10/30/2015 02:21 AM, Shannon Zhao wrote: >> From: Shannon Zhao <shannon.z...@linaro.org> >> >> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or >> reset_unknown

Re: [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/11/3 4:13, Christopher Covington wrote: > On 10/30/2015 02:21 AM, Shannon Zhao wrote: >> From: Shannon Zhao <shannon.z...@linaro.org> >> >> When we use tools like perf on host, perf passes the event type and the >> id of this event type category to

Re: [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/10/16 14:08, Wei Huang wrote: >> +/** >> > + * kvm_pmu_get_counter_value - get PMU counter value >> > + * @vcpu: The vcpu pointer >> > + * @select_idx: The counter index >> > + */ >> > +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 >> > select_idx) >> > +{ >> > +

Re: [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register

On 2015/10/16 23:06, Wei Huang wrote: > > > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >> Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its >> reset handler. Add a new case to emulate reading to PMCCNTR register. >> >> Signed-off-by: Shan

Re: [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

On 2015/10/16 23:25, Wei Huang wrote: >> /** >> > + * kvm_pmu_software_increment - do software increment >> > + * @vcpu: The vcpu pointer >> > + * @val: the value guest writes to PMSWINC register >> > + */ >> > +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) >> > +{ >> > + int

Re: [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/10/16 13:35, Wei Huang wrote: > > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >> > Add reset handler which gets host value of PMCR_EL0 and make writable >> > bits architecturally UNKNOWN. Add a common access handler for PMU >> > registers which emul

Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support

On 2015/10/17 1:01, Christopher Covington wrote: > On 10/16/2015 12:55 AM, Wei Huang wrote: >> > >> > >> > On 09/24/2015 05:31 PM, Shannon Zhao wrote: >>> >> This patchset adds guest PMU support for KVM on ARM64. It takes >>> >> trap

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

On 2015/9/14 19:53, Christoffer Dall wrote: Hi Shannon, On Fri, Sep 11, 2015 at 04:54:53PM +0800, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

les in struct kvm_pmc * Fix the handle of cp15 regs * Create a new kvm device vPMU, then userspace could choose whether to create PMU * Fix the handle of PMU overflow interrupt On 2015/9/11 16:54, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> This patchset adds guest PM

[PATCH v2 13/22] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- ar

Re: [PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu

On 2015/9/11 17:10, Marc Zyngier wrote: > On 11/09/15 09:54, Shannon Zhao wrote: >> From: Shannon Zhao <shannon.z...@linaro.org> >> >> Here we plan to support virtual PMU for guest by full software >> emulation, so define some basic structs and functions prep

[PATCH v2 10/22] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of th

[PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao <shannon.z...@linaro.org> When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. While we're trapping and emu

[PATCH v2 12/22] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf

[PATCH v2 05/22] KVM: ARM64: Add a helper for CP15 registers reset to UNKNOWN

From: Shannon Zhao <shannon.z...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index d411e25..a0b3811 100644 --- a/ar

[PATCH v2 01/22] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao <shannon.z...@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.pa...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> ---

[PATCH v2 17/22] KVM: ARM64: Add reset and access handlers for PMSWINC register

From: Shannon Zhao <shannon.z...@linaro.org> Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 18 +-

[PATCH v2 19/22] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao <shannon.z...@linaro.org> When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao <shannon.z...@l

[PATCH v2 18/22] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

From: Shannon Zhao <shannon.z...@linaro.org> Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 16

[PATCH v2 09/22] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_even

[PATCH v2 22/22] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao <shannon.z...@linaro.org> Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/ua

[PATCH v2 02/22] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao <shannon.z...@linaro.org> Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monito

[PATCH v2 07/22] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

From: Shannon Zhao <shannon.z...@linaro.org> Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys

[PATCH v2 15/22] KVM: ARM64: Add a helper for CP15 registers reset to specified value

From: Shannon Zhao <shannon.z...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.h | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index a0b3811..a476b1b 100644 --- a/ar

[PATCH v2 14/22] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kv

[PATCH v2 06/22] KVM: ARM64: Add reset and access handlers for PMSELR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Signed-off-by: Shanno

[PATCH v2 21/22] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao <shannon.z...@linaro.org> When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files

[PATCH v2 00/22] KVM: ARM64: Add guest PMU support

From: Shannon Zhao <shannon.z...@linaro.org> This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs

[PATCH v2 11/22] KVM: ARM64: Add reset and access handlers for PMCCNTR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading to PMCCNTR register. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 17

[PATCH v2 03/22] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao <shannon.z...@linaro.org> We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64

[PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao <shannon.z...@linaro.org> Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shanno

[PATCH v2 20/22] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao <shannon.z...@linaro.org> Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 18 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/kvm/re

[PATCH v2 16/22] KVM: ARM64: Add reset and access handlers for PMUSERENR register

From: Shannon Zhao <shannon.z...@linaro.org> Since the reset value of PMUSERENR is zero, use reset_val(_cp15) with zero for its reset handler. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/kvm/sys_regs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deleti

Re: [PATCH v2 08/22] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 2015/9/11 19:04, Marc Zyngier wrote: On 11/09/15 09:55, Shannon Zhao wrote: From: Shannon Zhao <shannon.z...@linaro.org> When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Wei, On 2015/9/17 5:07, Wei Huang wrote: > I am testing this series. Thanks for your time and help. > The first question is: do you plan to add ACPI > support in QEMU? To the completeness, this should be added. Maybe this could be added at v3. But I have a look at the kernel PMU driver, it

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Wei, On 2015/9/17 13:56, Wei Huang wrote: > > > On 09/16/2015 08:32 PM, Shannon Zhao wrote: >> Hi Wei, >> >> On 2015/9/17 5:07, Wei Huang wrote: >>> I am testing this series. >> Thanks for your time and help. >> >>> The first questio

Re: [PATCH v2 00/22] KVM: ARM64: Add guest PMU support

Hi Andrew, On 2015/9/17 17:30, Andrew Jones wrote: > On Thu, Sep 17, 2015 at 09:32:34AM +0800, Shannon Zhao wrote: >> > Hi Wei, >> > >> > On 2015/9/17 5:07, Wei Huang wrote: >>> > > I am testing this series. >> > Thanks for your time and

Re: [PATCH v2 04/22] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

On 2015/9/11 18:07, Marc Zyngier wrote: > On 11/09/15 09:54, Shannon Zhao wrote: >> > From: Shannon Zhao <shannon.z...@linaro.org> >> > >> > Add reset handler which gets host value of PMCR_EL0 and make writable >> > bits architecturally

[PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu

contains at most 32(ARMV8_MAX_COUNTERS) counters. Since this only supports ARM64 (or PMUv3), add a separate config symbol for it. Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Kconfig| 8 inclu

[PATCH v3 00/20] KVM: ARM64: Add guest PMU support

of adding alone handler for each register * Try to use the sys_regs to store the register value instead of adding new variables in struct kvm_pmc * Fix the handle of cp15 regs * Create a new kvm device vPMU, then userspace could choose whether to create PMU * Fix the handle of PMU overflow interrup

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