Anthony Liguori wrote:
For KVM, it should be okay as well. But we can replace two CR4 accesses
with just one hypercall.
I was thinking the same thing :-)
I was actually thinking about adding a hypercall to set/clear a bit in a
control register. The thought here is
Avi Kivity wrote:
Anthony Liguori wrote:
For KVM, it should be okay as well. But we can replace two CR4 accesses
with just one hypercall.
I was thinking the same thing :-)
I was actually thinking about adding a hypercall to set/clear a bit
in a control register. The
Regards,
Anthony Liguori
Subject: [PATCH][PARAVIRT] Eliminate unnecessary CR3 read in TLB flush
This patch eliminates the CR3 read (which would cause a VM exit) in the TLB
flush path. The patch is based on Ingo Molnar's paravirt series.
Signed-off-by: Anthony Liguori [EMAIL PROTECTED]
Index:
Andi Kleen wrote:
On Wednesday 30 May 2007 16:53:41 Anthony Liguori wrote:
Subject: [PATCH][PARAVIRT] Eliminate unnecessary CR3 read in TLB flush
This patch eliminates the CR3 read (which would cause a VM exit) in the TLB
flush path. The patch is based on Ingo Molnar's paravirt series.
Jeremy Fitzhardinge wrote:
Anthony Liguori wrote:
Sure. It adds a few more cycles onto native though (two memory
reads,
and some math).
As opposed to a serializing control-register read? I think that's
probably a win.
J
And actually you don't need the write to CR3 to flush TLB
Nakajima, Jun wrote:
And actually you don't need the write to CR3 to flush TLB because the
one to CR4 does it. Or does kvm_flush_tlb_kernel assume that CR3 is
updated at the same time?
Jun
It should not be necessary, but I believe this was added as a workaround
to a PII erratum. I can't
Zachary Amsden wrote:
Nakajima, Jun wrote:
And actually you don't need the write to CR3 to flush TLB because
the
one to CR4 does it. Or does kvm_flush_tlb_kernel assume that CR3 is
updated
at the same time?
Jun
It should not be necessary, but I believe this was added as a
Nakajima, Jun wrote:
Zachary Amsden wrote:
Nakajima, Jun wrote:
And actually you don't need the write to CR3 to flush TLB because
the
one to CR4 does it. Or does kvm_flush_tlb_kernel assume that CR3 is
updated
at the same time?
Jun
It should not
Anthony Liguori wrote:
Nakajima, Jun wrote:
snip
For KVM, it should be okay as well. But we can replace two CR4
accesses
with just one hypercall.
I was thinking the same thing :-)
I was actually thinking about adding a hypercall to set/clear a bit in
a
control register. The
Anthony Liguori wrote:
I was thinking the same thing :-)
I was actually thinking about adding a hypercall to set/clear a bit in
a control register. The thought here is that it would be useful not
just for the global bit but also for CR0.TS although we would need
another paravirt_op hook
Nakajima, Jun wrote:
Anthony Liguori wrote:
Given the optimizations for CPU virtualization in the current H/W, I'm
not sure if such hooks are useful. Do you have any performance data that
justify such hooks?
No, I don't. It was just a thought that was yet to be confirmed.
Regards,
On Wed, 2007-05-30 at 14:22 -0500, Anthony Liguori wrote:
I was actually thinking about adding a hypercall to set/clear a bit in a
control register. The thought here is that it would be useful not just
for the global bit but also for CR0.TS although we would need another
paravirt_op hook
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