On 28 January 2014 01:59, Scott Wood wrote:
> On Sat, 2014-01-25 at 03:15 +0100, Alexander Graf wrote:
>> Ok, let's go through the combinations for a 32-bit write of 0x01020304 on
>> PPC and what data[] looks like
>>
>> your proposal:
>>
>> BE guest, BE host: { 0x01, 0x02, 0x03, 0x04 }
>> LE
The KVM API documentation is not clear about the semantics of the data
field on the mmio struct on the kvm_run struct.
This has become problematic when supporting ARM guests on big-endian
host systems with guests of both endianness types, because it is unclear
how the data should be exported to us
Writing to IC is not allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_emulate.c | 3 +++
arch/powerpc/kvm/book3s_pr.c| 2 ++
3 files changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/kvm
We ignore write to these registers now
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index bf6b11021250..c0aee34ef04f 100644
--- a/arch/p
We don't have SMT support yet, hence we should not find a doorbell
message generated
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.
We allow priv-mode update of this. The guest value is saved in fscr,
and the value actually used is saved in shadow_fscr. shadow_fscr
only contains values that are allowed by the host. On
facility unavailable interrupt, if the facility is allowed by fscr
but disabled in shadow_fscr we need to emula
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_asm.h | 4 +++-
arch/powerpc/kvm/book3s.c | 4
arch/powerpc/kvm/book3s_emulate.c | 18 ++
Since we don't support SMT yet, we should always find zero in
Directed privileged doorbell exception state register.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/k
Since PR KVM doesn't support SMT yet, we always return 0.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index abe6f3057e5b..e74dda36ebea 100644
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.c | 16
arch/pow
Hello,
This patch series implements PR KVM support for POWER8 platform
-aneesh
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virtual time base register is a per vm register and need to saved
and restored on vm exit and entry. Writing to VTB is not allowed
in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/reg.h | 7 +++
arch/powerp
Runtime disable transactional memory feature looking at pa-features
device tree entry. We need to do this so that we can run a kernel
built with TM config in PR mode. For PR guest we provide a device
tree entry with TM feature disabled in pa-features
Signed-off-by: Aneesh Kumar K.V
---
arch/powe
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