[PATCH 0/2] Fixes for HV KVM on PPC for 3.14

These two patches fix two things in hypervisor-mode KVM for the IBM POWER server processors. The first patch removes a hunk of extraneous code that got in as a result of a mistake I made in cleaning up after rebasing a patch. The second fixes a bug that causes host memory corruption. Both

Re: [PATCH 0/2] Fixes for HV KVM on PPC for 3.14

On Thu, 2014-03-13 at 20:01 +1100, Paul Mackerras wrote: These two patches fix two things in hypervisor-mode KVM for the IBM POWER server processors. The first patch removes a hunk of extraneous code that got in as a result of a mistake I made in cleaning up after rebasing a patch. The

[PATCH 05/10] powerpc/booke64: Use SPRG7 for VDSO

Previously SPRG3 was marked for use by both VDSO and critical interrupts (though critical interrupts were not fully implemented). In commit 8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad (powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss crit int), Mihai Caraman made an attempt to resolve this

[PATCH 06/10] powerpc/booke64: Use SPRG_TLB_EXFRAME on bolted handlers

While bolted handlers (including e6500) do not need to deal with a TLB miss recursively causing another TLB miss, nested TLB misses can still happen with crit/mc/debug exceptions -- so we still need to honor SPRG_TLB_EXFRAME. We don't need to spend time modifying it in the TLB miss fastpath,

Re: [PATCH v3] KVM: Specify byte order for KVM_EXIT_MMIO

On Tue, Jan 28, 2014 at 08:28:42AM -0800, Christoffer Dall wrote: The KVM API documentation is not clear about the semantics of the data field on the mmio struct on the kvm_run struct. This has become problematic when supporting ARM guests on big-endian host systems with guests of both