> In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
> Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread
s/TID/TIR/ above
> per core, we can just always expose 0 here.
I'm not sure if we ever do, but if we IPI ourselves using a doorbell,
we'll ne
> This patch series implements split core mode on POWER8. This enables up to 4
> subcores per core which can each independently run guests (per guest SPRs like
> SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this
> feature in the code and commit messages.
>
> Most of th
POWER8 introduces a new facility called the "Event Based Branch" facility.
It contains of a few registers that indicate where a guest should branch to
when a defined event occurs and it's in PR mode.
We don't want to really enable EBB as it will create a big mess with !PR guest
mode while hardware
POWER8 implements a new register called TAR. This register has to be
enabled in FSCR and then from KVM's point of view is mere storage.
This patch enables the guest to use TAR.
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_host.h | 2 ++
arch/powerpc/kvm/book3s.c |
When running on a POWER8 host, we get away with running the guest as POWER7
and nothing falls apart.
However, when we start exposing POWER8 as guest CPU, guests will start using
new abilities on POWER8 which we need to handle.
This patch set does a minimalistic approach to implementing those bits
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_
POWER8 introduced a new interrupt type called "Facility unavailable interrupt"
which contains its status message in a new register called FSCR.
Handle these exits and try to emulate instructions for unhandled facilities.
Follow-on patches enable KVM to expose specific facilities into the guest.
S
In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 1 +
1 file changed, 1 insertio
When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
that we don't emulate. Just ignore accesses to them.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
On 28.04.14 16:19, Christian Zigotzky wrote:
Hi Alex,
Thanks a lot for your answer. I checked dmesg yesterday but I didn't
find any error messages about MOL or KVM. I played a bit with the
emulated CPU types but without any success. I tried the VNC output and
it works but it didn't solve the
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