Re: [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register

> In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a > Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread s/TID/TIR/ above > per core, we can just always expose 0 here. I'm not sure if we ever do, but if we IPI ourselves using a doorbell, we'll ne

Re: [PATCH 0/6] Implement split core for POWER8

> This patch series implements split core mode on POWER8. This enables up to 4 > subcores per core which can each independently run guests (per guest SPRs like > SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this > feature in the code and commit messages. > > Most of th

[PATCH 5/6] KVM: PPC: Book3S PR: Expose EBB registers

POWER8 introduces a new facility called the "Event Based Branch" facility. It contains of a few registers that indicate where a guest should branch to when a defined event occurs and it's in PR mode. We don't want to really enable EBB as it will create a big mess with !PR guest mode while hardware

[PATCH 4/6] KVM: PPC: Book3S PR: Expose TAR facility to guest

POWER8 implements a new register called TAR. This register has to be enabled in FSCR and then from KVM's point of view is mere storage. This patch enables the guest to use TAR. Signed-off-by: Alexander Graf --- arch/powerpc/include/asm/kvm_host.h | 2 ++ arch/powerpc/kvm/book3s.c |

[PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

When running on a POWER8 host, we get away with running the guest as POWER7 and nothing falls apart. However, when we start exposing POWER8 as guest CPU, guests will start using new abilities on POWER8 which we need to handle. This patch set does a minimalistic approach to implementing those bits

[PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

POWER8 introduces transactional memory which brings along a number of new registers and MSR bits. Implementing all of those is a pretty big headache, so for now let's at least emulate enough to make Linux's context switching code happy. Signed-off-by: Alexander Graf --- arch/powerpc/kvm/book3s_

[PATCH 3/6] KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR

POWER8 introduced a new interrupt type called "Facility unavailable interrupt" which contains its status message in a new register called FSCR. Handle these exits and try to emulate instructions for unhandled facilities. Follow-on patches enable KVM to expose specific facilities into the guest. S

[PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register

In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread per core, we can just always expose 0 here. Signed-off-by: Alexander Graf --- arch/powerpc/kvm/book3s_emulate.c | 1 + 1 file changed, 1 insertio

[PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs that we don't emulate. Just ignore accesses to them. Signed-off-by: Alexander Graf --- arch/powerpc/kvm/book3s_emulate.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/book3s_emulate.c

Re: Does KVM support the P.A. Semi PA6T cpu?

On 28.04.14 16:19, Christian Zigotzky wrote: Hi Alex, Thanks a lot for your answer. I checked dmesg yesterday but I didn't find any error messages about MOL or KVM. I played a bit with the emulated CPU types but without any success. I tried the VNC output and it works but it didn't solve the