On 06.05.14 06:26, Gavin Shan wrote:
On Mon, May 05, 2014 at 08:00:12AM -0600, Alex Williamson wrote:
On Mon, 2014-05-05 at 13:56 +0200, Alexander Graf wrote:
On 05/05/2014 03:27 AM, Gavin Shan wrote:
The series of patches intends to support EEH for PCI devices, which have been
passed
On 06.05.14 02:41, Paul Mackerras wrote:
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu-arch.fault_dar;
How about PA6T and G5s?
G5 sets DAR on an alignment interrupt.
As for
On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
Isn't this a greater problem? We should start swapping before we hit
the point where non movable kernel allocation fails, no?
Possibly but the fact remains, this can be avoided by making
On Tue, 2014-05-06 at 08:56 +0200, Alexander Graf wrote:
For the error injection, I guess I have to put the logic token
management
into QEMU and error injection request will be handled by QEMU and
then
routed to host kernel via additional syscall as we did for pSeries.
Yes, start off
On Tue, 2014-05-06 at 09:05 +0200, Alexander Graf wrote:
On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
Isn't this a greater problem? We should start swapping before we hit
the point where non movable kernel allocation fails, no?
On 06.05.14 09:19, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 09:05 +0200, Alexander Graf wrote:
On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
Isn't this a greater problem? We should start swapping before we hit
the point
On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s_64.h | 146 ++-
arch/powerpc/kvm/book3s_hv.c | 7 ++
2 files changed, 130 insertions(+), 23
On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
So if I understand this patch correctly, it simply introduces logic to
handle page sizes other than 4k, 64k, 16M by analyzing the actual page
size field in the HPTE. Mind to explain why exactly that enables us to
use THP?
What
Alexander Graf ag...@suse.de writes:
On 06.05.14 02:41, Paul Mackerras wrote:
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return vcpu-arch.fault_dar;
How about PA6T and G5s?
G5 sets DAR on
Alexander Graf ag...@suse.de writes:
On 06.05.14 09:19, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 09:05 +0200, Alexander Graf wrote:
On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf wrote:
Isn't this a greater problem? We should
On 05/06/2014 04:12 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 06.05.14 02:41, Paul Mackerras wrote:
On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote:
On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote:
+#ifdef CONFIG_PPC_BOOK3S_64
+ return
Alexander Graf ag...@suse.de writes:
On 05/04/2014 07:30 PM, Aneesh Kumar K.V wrote:
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
static inline unsigned long hpte_page_size(unsigned long h, unsigned long
l)
{
+int size, a_size;
+/* Look at the 8
On 05/06/2014 04:20 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 06.05.14 09:19, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 09:05 +0200, Alexander Graf wrote:
On 06.05.14 02:06, Benjamin Herrenschmidt wrote:
On Mon, 2014-05-05 at 17:16 +0200, Alexander Graf
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
* Changes from V4
* Update comments around using fault_dar
arch/powerpc/include/asm/disassemble.h |
Alexander Graf ag...@suse.de writes:
On 05/06/2014 11:26 AM, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
.
I updated the commit message as below. Let me know if this is ok.
KVM: PPC: BOOK3S: HV: THP support for guest
On recent IBM
On 05/06/2014 05:06 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/06/2014 11:26 AM, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
.
I updated the commit message as below. Let me know if this is ok.
KVM: PPC:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Sunday, May 04, 2014 1:14 AM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v2 1/4] KVM: PPC: e500mc: Revert add load inst
On 05/06/2014 05:48 PM, mihai.cara...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Sunday, May 04, 2014 1:14 AM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re:
Today when KVM tries to reserve memory for the hash page table it
allocates from the normal page allocator first. If that fails it
falls back to CMA's reserved region. One of the side effects of
this is that we could end up exhausting the page allocator and
get linux into OOM conditions while we
On 05/06/2014 06:08 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/06/2014 05:06 PM, Aneesh Kumar K.V wrote:
Alexander Graf ag...@suse.de writes:
On 05/06/2014 11:26 AM, Benjamin Herrenschmidt wrote:
On Tue, 2014-05-06 at 11:12 +0200, Alexander Graf wrote:
.
On recent IBM Power CPUs, while the hashed page table is looked up using
the page size from the segmentation hardware (i.e. the SLB), it is
possible to have the HPT entry indicate a larger page size. Thus for
example it is possible to put a 16MB page in a 64kB segment, but since
the hash lookup
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Friday, May 02, 2014 12:55 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v2 3/4] KVM: PPC: Alow kvmppc_get_last_inst() to
On Tue, 2014-05-06 at 21:38 +0530, Aneesh Kumar K.V wrote:
I updated the commit message as below. Let me know if this is ok.
KVM: PPC: BOOK3S: HV: THP support for guest
This has nothing to do with THP.
THP support in guest depend on KVM advertising MPSS feature. We already
have
On Sun, May 04, 2014 at 10:56:08PM +0530, Aneesh Kumar K.V wrote:
With debug option sleep inside atomic section checking enabled we get
the below WARN_ON during a PR KVM boot. This is because upstream now
have PREEMPT_COUNT enabled even if we have preempt disabled. Fix the
warning by adding
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