ePAPR represents hardware threads as cpu node properties in device tree.
So with existing QEMU, hardware threads are simply exposed as vcpus with
one hardware thread.
The e6500 core shares TLBs between hardware threads. Without tlb write
conditional instruction, the Linux kernel uses per core mech
Commits e4d57e1ee1ab (KVM: Move irq notifier implementation into
eventfd.c, 2014-06-30) included the irq notifier code unconditionally
in eventfd.c, while it was under CONFIG_HAVE_KVM_IRQCHIP before.
Similarly, commit 297e21053a52 (KVM: Give IRQFD its own separate enabling
Kconfig option, 2014-06-
Il 05/08/2014 14:27, Paolo Bonzini ha scritto:
> Il 30/06/2014 12:51, Paul Mackerras ha scritto:
>> This series of patches provides a way to implement IRQFD support
>> without having to implement IRQ routing, and adds IRQFD support for
>> the XICS interrupt controller emulation. (XICS is the inter
Though SPE/AltiVec shares interrupts numbers on BookE cores, use distinct
defines to identify these numbers. This improves code readability especially
in KVM.
Revert c58ce397 and 6b310fc5 patches that added common defines.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kernel/exceptions-64e.S |
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai Caraman
