[PATCH v2 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

SPE exception handlers are now defined for 32-bit e500mc cores even though SPE unit is not present and CONFIG_SPE is undefined. Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE and consequently guard __stup_ivors and __setup_cpu functions. Signed-off-by: Mihai Caraman

[PATCH v2 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

Book3E specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2 cores while AltiVec is present in e6500 core. So we can currently decide at compile-time which unit to support exclusively. As Alexander Graf suggested, this will improve code readab

[PATCH v4 0/6] KVM: PPC: Book3e: AltiVec support

Add KVM Book3e AltiVec support. Changes: v4: - use CONFIG_SPE_POSSIBLE and a new ifdef for CONFIG_ALTIVEC - remove SPE handlers from bookehv - split ONE_REG powerpc generic and ONE_REG AltiVec - add setters for IVPR, IVOR2 and IVOR8 - add api documentation for ONE_REG IVPR and IVORs - don't

[PATCH v4 6/6] KVM: PPC: Booke: Add ONE_REG support for IVPR and IVORs

Add ONE_REG support for IVPR and IVORs registers. Implement IVPR, IVORs 0-15 and 35 in booke common layer. Signed-off-by: Mihai Caraman --- v4: - add ONE_REG IVPR - use IVPR, IVOR2 and IVOR8 setters - add api documentation for ONE_REG IVPR and IVORs v3: - new patch Documentation/virtual/kv

[PATCH v4 3/6] KVM: PPC: Make ONE_REG powerpc generic

Make ONE_REG generic for server and embedded architectures by moving kvm_vcpu_ioctl_get_one_reg() and kvm_vcpu_ioctl_set_one_reg() functions to powerpc layer. Signed-off-by: Mihai Caraman --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG AltiVec support powerpc gen

[PATCH v4 4/6] KVM: PPC: Move ONE_REG AltiVec support to powerpc

Move ONE_REG AltiVec support to powerpc generic layer. Signed-off-by: Mihai Caraman --- v4: - split ONE_REG powerpc generic and ONE_REG AltiVec v3: - make ONE_REG AltiVec support powerpc generic v2: - add comment describing VCSR register representation in KVM vs kernel arch/powerpc/include

[PATCH v4 2/6] KVM: PPC: Book3e: Add AltiVec support

Add AltiVec support in KVM for Book3e. FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Book3e specification defines shared interrupt numbers for SPE and AltiVec units. Still SPE is present in e200/e500v2 cores while AltiVec is present in e6500 core. So we

[PATCH v4 1/6] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by loading the guest state into the unit before entering the guest instead of doing it on each vcpu schedule. Without this improvement an interrupt may claim floating point corrupting guest state. Signed-off-by: Mihai Caraman --- v4: - update commit message v3: - no chang

[PATCH v4 5/6] KVM: PPC: Booke: Add setter functions for IVPR, IVOR2 and IVOR8 emulation

Add setter functions for IVPR, IVOR2 and IVOR8 emulation in preparation for ONE_REG support. Signed-off-by: Mihai Caraman --- v4: - new patch - add api documentation for ONE_REG IVPR and IVORs arch/powerpc/kvm/booke.c | 24 arch/powerpc/kvm/booke.h |

Re: [PATCH v2 1/2] powerpc/booke: Restrict SPE exception handlers to e200/e500 cores

On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote: > SPE exception handlers are now defined for 32-bit e500mc cores even though > SPE unit is not present and CONFIG_SPE is undefined. > > Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE > and consequently guard __s

Re: [PATCH v2 2/2] powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers

On Wed, 2014-08-20 at 16:09 +0300, Mihai Caraman wrote: > Book3E specification defines shared interrupt numbers for SPE and AltiVec > units. Still SPE is present in e200/e500v2 cores while AltiVec is present in > e6500 core. So we can currently decide at compile-time which unit to support > exclusi