context switch (non-lazily), so
the only remaining bit is to save it between qemu and the guest.
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
This is a resending of http://www.spinics.net/lists/kvm-ppc/msg02707.html
arch/powerpc/include/asm/kvm_host.h |6 ++
arch/powerpc/include/asm
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500 does not have real mode.
Signed-off-by:
This is in line with what other architectures do, and will allow us to
map things other than ordinary, unreserved kernel pages -- such as
dedicated devices, or large contiguous reserved regions.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |2 -
arch/powerpc/kvm
where devices are directly assigned on chips without an
IOMMU -- in these cases, we need guest physical and true physical to
match, and be contiguous, so static reservation and mapping via /dev/mem
is the most straightforward way to set things up.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_
This avoids races. It also means that we use the shadow TLB way,
rather than the hardware hint -- if this is a problem, we could do
a tlbsx before inserting a TLB0 entry.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 26 +-
1 files changed, 13 insertions
From: Liu Yu
This patch utilize PID1 to map guest ID to shadow ID,
so that we can combine all needs to invalidate host TLB together,
and therefor reduce the frequency of calling _tlbia().
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |8 +-
arch
On Thu, 19 May 2011 16:10:48 +0200
Alexander Graf wrote:
> On 05/18/2011 01:42 AM, Scott Wood wrote:
> > +For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
>
> Can we rename those KVM_MMU_BOOKE_206_NOHV and KVM_MMU_BOOKE_206_HV?
> Same for the function names. I
On Thu, 19 May 2011 12:43:21 +0200
Alexander Graf wrote:
> On 05/18/2011 01:42 AM, Scott Wood wrote:
> > +void kvmppc_map_magic(struct kvm_vcpu *vcpu)
> > +{
> > + struct tlbe magic;
> > + ulong shared_page = ((ulong)vcpu->arch.shared)& PAGE_MASK;
&g
On Thu, 19 May 2011 12:05:57 +0200
Alexander Graf wrote:
> On 05/18/2011 01:40 AM, Scott Wood wrote:
> > BKeep the guest MSR and the guest-mode true MSR separate, rather than
>
> Bkeep?
Doh.
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> > in
On Thu, 19 May 2011 19:37:05 +0200
Alexander Graf wrote:
>
> On 19.05.2011, at 18:28, Scott Wood wrote:
>
> > On Thu, 19 May 2011 16:10:48 +0200
> > Alexander Graf wrote:
> >
> >> On 05/18/2011 01:42 AM, Scott Wood wrote:
> >>> +For mmu types
On Thu, 19 May 2011 15:18:30 +0200
Alexander Graf wrote:
> On 05/18/2011 01:42 AM, Scott Wood wrote:
> > +static inline int local_sid_setup_one(struct id *entry)
> > +{
> > + unsigned long sid;
> > + int ret = -1;
> > +
> > + sid = ++(__get_c
On Sat, 21 May 2011 18:39:01 +0200
Alexander Graf wrote:
> Btw - have you considered moving the MAS registers into the shared page now
> that it's available on BookE? That should give quite a significant
> performance boost :)
That's in the next patchset (among other paravirt stuff). :-)
-Sco
Yu (2):
KVM: PPC: e500: Stop keeping shadow TLB
KVM: PPC: e500: Add shadow PID support
Scott Wood (10):
powerpc/e500: SPE register saving: take arbitrary struct offset
KVM: PPC: booke: use shadow_msr
KVM: PPC: e500: Save/restore SPE state
KVM: PPC: e500: Disable preloading TLB1 in tlb
().
This patch moves SPEFSCR saving to flush_spe_to_thread(),
and cleans up the caller that needs to save SPEFSCR accordingly.
Signed-off-by: Liu Yu
Acked-by: Kumar Gala
Signed-off-by: Scott Wood
---
arch/powerpc/kernel/head_fsl_booke.S |2 --
arch/powerpc/kernel/process.c|1
Previously, these macros hardcoded THREAD_EVR0 as the base of the save
area, relative to the base register passed. This base offset is now
passed as a separate macro parameter, allowing reuse with other SPE
save areas, such as used by KVM.
Acked-by: Kumar Gala
Signed-off-by: Scott Wood
c_set_msr().
While we're modifying the guest entry code, reorder a few instructions
to bury some load latencies.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_host.h |2 +-
arch/powerpc/kernel/asm-offsets.c |2 +-
arch/powerpc/kvm/booke.c|1 +
ar
Since TLB1 loading doesn't check the shadow TLB before allocating another
entry, you can get duplicates.
Once shadow PIDs are enabled in a later patch, we won't need to
invalidate the TLB on every switch, so this optimization won't be
needed anyway.
Signed-off-by: Scott Wood
--
context switch (non-lazily), so
the only remaining bit is to save it between qemu and the guest.
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_host.h |6 ++
arch/powerpc/include/asm/reg_booke.h |1 +
arch/powerpc/kernel/asm-offsets.c|7 +++
arch
This avoids races. It also means that we use the shadow TLB way,
rather than the hardware hint -- if this is a problem, we could do
a tlbsx before inserting a TLB0 entry.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 26 +-
1 files changed, 13 insertions
where devices are directly assigned on chips without an
IOMMU -- in these cases, we need guest physical and true physical to
match, and be contiguous, so static reservation and mapping via /dev/mem
is the most straightforward way to set things up.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500 does not have real mode.
Signed-off-by:
This is in line with what other architectures do, and will allow us to
map things other than ordinary, unreserved kernel pages -- such as
dedicated devices, or large contiguous reserved regions.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |2 -
arch/powerpc/kvm
From: Liu Yu
Instead of a fully separate set of TLB entries, keep just the
pfn and dirty status.
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h | 20 ++-
arch/powerpc/kvm/e500_tlb.c | 317 +++---
2 files changed
Only look in the 4 entries that could possibly contain the
entry we're looking for.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |8 +-
arch/powerpc/include/asm/kvm_host.h |1 +
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kvm/44x_tlb.c |4 +-
arch/powerpc/kvm/booke.c| 11 +-
arch/powerpc/kvm/booke.h
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood
---
Documentation/virtual/kvm/api.txt | 84 +++-
arch/powerpc/include/asm/kvm.h | 35 +++
arch/powerpc/include/asm/kvm_e500.h | 23 +-
arch/powerpc/includ
On Sat, 4 Jun 2011 01:59:34 +0200
Alexander Graf wrote:
>
> On 03.06.2011, at 01:15, Scott Wood wrote:
>
> > This patchset contains SPE state management for e500 KVM guests, as well
> > as MMU enhancements (performance, userspace visibility, and support for
> >
On Tue, 14 Jun 2011 11:39:06 +0200
Alexander Graf wrote:
>
> On 03.06.2011, at 01:16, Scott Wood wrote:
>
> > diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
> > index 318dbc6..43923c3 100644
> > --- a/arch/powerpc/kvm/e500.c
> > +++ b/arch/po
On Tue, 14 Jun 2011 11:55:11 +0200
Alexander Graf wrote:
>
> On 03.06.2011, at 01:17, Scott Wood wrote:
>
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> > index e1d368c..45ad454 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/
On Tue, 14 Jun 2011 12:40:22 +0200
Alexander Graf wrote:
>
> On 03.06.2011, at 01:17, Scott Wood wrote:
>
> > diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
> > index c09e642..9d1e28d 100644
> > --- a/arch/powerpc/kvm/e500_tlb.c
> >
On Tue, 14 Jun 2011 12:41:03 +0200
Alexander Graf wrote:
>
> On 03.06.2011, at 01:17, Scott Wood wrote:
>
> > +static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500
> > *vcpu_e500,
> > +int tlbsel, int esel)
> &
c_set_msr().
While we're modifying the guest entry code, reorder a few instructions
to bury some load latencies.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_host.h |2 +-
arch/powerpc/kernel/asm-offsets.c |2 +-
arch/powerpc/kvm/booke.c|1 +
ar
Previously, these macros hardcoded THREAD_EVR0 as the base of the save
area, relative to the base register passed. This base offset is now
passed as a separate macro parameter, allowing reuse with other SPE
save areas, such as used by KVM.
Acked-by: Kumar Gala
Signed-off-by: Scott Wood
This avoids races. It also means that we use the shadow TLB way,
rather than the hardware hint -- if this is a problem, we could do
a tlbsx before inserting a TLB0 entry.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 26 +-
1 files changed, 13 insertions
context switch (non-lazily), so
the only remaining bit is to save it between qemu and the guest.
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
v3: removed mismerge hunk that removed
kvmppc_core_load_host/guest_debugstate stubs.
arch/powerpc/include/asm/kvm_host.h |6 ++
arch/powerpc
Since TLB1 loading doesn't check the shadow TLB before allocating another
entry, you can get duplicates.
Once shadow PIDs are enabled in a later patch, we won't need to
invalidate the TLB on every switch, so this optimization won't be
needed anyway.
Signed-off-by: Scott Wood
--
This is a shared page used for paravirtualization. It is always present
in the guest kernel's effective address space at the address indicated
by the hypercall that enables it.
The physical address specified by the hypercall is not used, as
e500 does not have real mode.
Signed-off-by:
This is in line with what other architectures do, and will allow us to
map things other than ordinary, unreserved kernel pages -- such as
dedicated devices, or large contiguous reserved regions.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |2 -
arch/powerpc/kvm
where devices are directly assigned on chips without an
IOMMU -- in these cases, we need guest physical and true physical to
match, and be contiguous, so static reservation and mapping via /dev/mem
is the most straightforward way to set things up.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_
From: Liu Yu
Instead of a fully separate set of TLB entries, keep just the
pfn and dirty status.
Signed-off-by: Liu Yu
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h | 20 ++-
arch/powerpc/kvm/e500_tlb.c | 317 +++---
2 files changed
ebase, and minor fixes in patches 4, 9, and 11.
Liu Yu (2):
KVM: PPC: e500: Stop keeping shadow TLB
KVM: PPC: e500: Add shadow PID support
Scott Wood (10):
powerpc/e500: SPE register saving: take arbitrary struct offset
KVM: PPC: booke: use shadow_msr
KVM: PPC: e500: Save/restore SPE
Only look in the 4 entries that could possibly contain the
entry we're looking for.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood
---
Documentation/virtual/kvm/api.txt | 84 +++-
arch/powerpc/include/asm/kvm.h | 35 +++
arch/powerpc/include/asm/kvm_e500.h | 23 +-
arch/powerpc/includ
Signed-off-by: Scott Wood
---
v3: fix comment typo
arch/powerpc/include/asm/kvm_e500.h |8 +-
arch/powerpc/include/asm/kvm_host.h |1 +
arch/powerpc/kernel/asm-offsets.c |1 +
arch/powerpc/kvm/44x_tlb.c |4 +-
arch/powerpc/kvm/booke.c| 11 +-
arch/powerpc
On Wed, 15 Jun 2011 13:34:06 +0200
Alexander Graf wrote:
>
> On 15.06.2011, at 12:50, Alexander Graf wrote:
> > What are your results when using the magic page? I have the following
> > numbers with your patches applied:
> >
> > == bare metal ==
> >
> > root@e500:~/kvm# time for i in {1..1000
On Wed, 15 Jun 2011 23:21:37 +0200
Alexander Graf wrote:
>
> On 15.06.2011, at 22:58, Scott Wood wrote:
>
> > With paravirt including my local patches (but still no large pages):
>
> Do these include patches to move the MAS registers to the shared page? That
> shoul
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood
---
v4: fix the encoding of a fully associative array to be
ways = size rather than ways = 0. Previously docs had been
changed, but not code.
No change in the rest of the pat
On Fri, 17 Jun 2011 16:33:56 +0200
Alexander Graf wrote:
>
> On 17.06.2011, at 00:29, Scott Wood wrote:
>
> > This implements a shared-memory API for giving host userspace access to
> > the guest's TLB.
>
> Would you mind if we wait with applying th
It should contain the way, not the absolute TLB0 index.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 13c432e..2e99d66 100644
--- a/arch/powerpc
Delay allocation of the shadow pid until we're ready to disable
preemption and write the entry.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c | 36 +++-
1 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tl
. For the guest
TLB0 entries, we still track it with gtlb_priv, to avoid having to
retranslate if the entry is evicted from the host TLB but not the
guest TLB.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h | 20 +++-
arch/powerpc/include/asm/mmu-book3e.h |1 +
arch
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood
---
v5:
- respin on top of fixes
- remove unused kvm_dump_tlbs() now that there's another way to get the
data
- clarify in the documentation that even though hardwa
Scott Wood (5):
KVM: PPC: e500: tlbsx: fix tlb0 esel
KVM: PPC: e500: don't translate gfn to pfn with preemption disabled
KVM: PPC: e500: Eliminate preempt_disable in local_sid_destroy_all
KVM: PPC: e500: clear up confusion between host and guest entries
KVM: PPC: e500: MM
The only place it makes sense to call this function already needs
to have preemption disabled.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/e500_tlb.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index
On Fri, 8 Jul 2011 20:33:18 +
Aashish Mittal wrote:
> Hi
>
> I'm trying to emulate the lwz instruction in powerpc e500 kvm for my project
> .
> And the instruction can modify any of the 32 gpr's . So i'm resuming the
> guest
> using RESUME_GUEST_NV Flag so that all the gpr's can be updat
On Sat, 9 Jul 2011 02:54:21 +0530
Aashish Mittal wrote:
> Hi Scot
> I'm working on kvm version 2.6.39 . So my project requires that i put a
> trace on a page in booke architecture (i.e removing the read and write
> privileges of that page) which causes all the instructions that try to read
> or w
On Mon, 18 Jul 2011 11:16:10 +0200
Alexander Graf wrote:
>
> On 08.07.2011, at 01:41, Scott Wood wrote:
>
> > It should contain the way, not the absolute TLB0 index.
> >
> > Signed-off-by: Scott Wood
> > ---
> > arch/powerpc/kvm/e500_tlb.c |3 +++
On Mon, 18 Jul 2011 12:09:53 +0200
Alexander Graf wrote:
> On 08.07.2011, at 01:41, Scott Wood wrote:
>
> > +void kvmppc_core_heavy_exit(struct kvm_vcpu *vcpu)
> > +{
> > + struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
> > + int i;
> > +
> >
On Mon, 18 Jul 2011 18:30:51 +0200
Alexander Graf wrote:
>
> On 18.07.2011, at 18:12, Scott Wood wrote:
>
> > On Mon, 18 Jul 2011 11:16:10 +0200
> > Alexander Graf wrote:
> >
> >>
> >> On 08.07.2011, at 01:41, Scott Wood wrote:
> >>
On Mon, 18 Jul 2011 18:33:58 +0200
Alexander Graf wrote:
>
> On 18.07.2011, at 18:18, Scott Wood wrote:
>
> > They're pinned by get_user_pages_fast(). We (potentially) write to them, so
> > we should mark them dirty, because they are dirty. It's up to the re
On Mon, 18 Jul 2011 11:49:10 +0200
Alexander Graf wrote:
> On 08.07.2011, at 01:41, Scott Wood wrote:
>
> > @@ -63,7 +64,9 @@ static DEFINE_PER_CPU(struct pcpu_id_table, pcpu_sids);
> > * The valid range of shadow ID is [1..255] */
> > static DEFINE_PER_CPU(unsigned
On Mon, 18 Jul 2011 23:37:50 +0200
Alexander Graf wrote:
> I guess I'm merely not understanding why we have the non-way bits set in TLB0
> entries, but not in TLB1 ones :). Do we pass in the real array index?
KVM internally uses the full TLB index (and unfortunately calls it esel) in
some place
On Mon, 18 Jul 2011 23:49:57 +0200
Alexander Graf wrote:
>
> On 18.07.2011, at 23:43, Scott Wood wrote:
>
> > On Mon, 18 Jul 2011 23:37:50 +0200
> > Alexander Graf wrote:
> >
> >> I guess I'm merely not understanding why we have the non-way bits s
On Sun, 24 Jul 2011 11:16:32 +0200
Alexander Graf wrote:
> On 19.07.2011, at 13:20, Johannes Weiner wrote:
>
> > You don't have to work around the mm subsystem trying to reclaim your
> > memory,
The pages are pinned by get_free_pages_fast().
> > maintain disk coherency that is guaranteed by th
On 08/08/2011 03:49 AM, Johannes Weiner wrote:
> On Mon, Jul 25, 2011 at 11:50:50PM +0200, Alexander Graf wrote:
>>
>> Well, alternatively we could simply bail out if the memory is not
>> anonymous, right? Then the pinning on get_user_pages_fast should be
>> enough. Johannes, would there be any dow
On 08/13/2011 10:14 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2011-07-18 at 11:18 -0500, Scott Wood wrote:
>
>>> Does this work? Why do we need to set them dirty in the first place? If the
>>> shared tlb pages are on file backed storage, we're screwed under memory
On 08/15/2011 10:15 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2011-08-15 at 10:03 -0500, Scott Wood wrote:
>> On 08/13/2011 10:14 AM, Benjamin Herrenschmidt wrote:
>>> On Mon, 2011-07-18 at 11:18 -0500, Scott Wood wrote:
>>>
>>>>> Does this work? Why
Delay allocation of the shadow pid until we're ready to disable
preemption and write the entry.
Signed-off-by: Scott Wood
---
v2: no changes (was 2/5 in v1)
arch/powerpc/kvm/e500_tlb.c | 36 +++-
1 files changed, 23 insertions(+), 13 deletions(-)
diff --
. For the guest
TLB0 entries, we still track it with gtlb_priv, to avoid having to
retranslate if the entry is evicted from the host TLB but not the
guest TLB.
Signed-off-by: Scott Wood
---
v2: Use a common struct for tlb parameters, which will be reused for
the guest tlb in the next patch. Fix
The only place it makes sense to call this function already needs
to have preemption disabled.
Signed-off-by: Scott Wood
---
v2: no changes (was 3/5 in v1)
arch/powerpc/kvm/e500_tlb.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch
This implements a shared-memory API for giving host userspace access to
the guest's TLB.
Signed-off-by: Scott Wood
---
v2: Use KVM_ENABLE_CAP instead of KVM_CONFIG_TLB.
Use kvmppc_e500_tlb_params instead of ad-hoc data representation.
Don't bother dirtying the pages on heavyweigh
It should contain the way, not the absolute TLB0 index.
Signed-off-by: Scott Wood
---
v2 (was 1/5 in v1): Now that we have gtlb_params[], no need
to special-case TLB0 (though the masking is a no-op for TLB1).
arch/powerpc/kvm/e500_tlb.c |2 ++
1 files changed, 2 insertions(+), 0 deletions
Scott Wood (5):
KVM: PPC: e500: don't translate gfn to pfn with preemption disabled
KVM: PPC: e500: Eliminate preempt_disable in local_sid_destroy_all
KVM: PPC: e500: clear up confusion between host and guest entries
KVM: PPC: e500: MMU API
KVM: PPC: e500: tlbsx: fix tlb0
On 08/25/2011 04:31 AM, Aashish Mittal wrote:
> I checked the memory by reading the guest page at the modified instruction
> and
> it is the modified instruction . I think the reason i'm not getting the EXIT
> is
> because the icache is not getting flushed properly.
> I'm trying to to flush th
Apply after "KVM: PPC: e500: TLB fixes and MMU API":
http://www.spinics.net/lists/kvm-ppc/msg03055.html
Liu Yu (1):
KVM: PPC: booke: Improve timer register emulation
Scott Wood (4):
KVM: PPC: booke: Fix int_pending calculation for MSR[EE] paravirt
KVM: PPC: booke: Paravirtua
int_pending was only being lowered if a bit in pending_exceptions
was cleared during exception delivery -- but for interrupts, we clear
it during IACK/TSR emulation. This caused paravirt for enabling
MSR[EE] to be ineffective.
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/booke.c |6
Also fix wrteei 1 paravirt to check for a pending interrupt.
Signed-off-by: Scott Wood
---
arch/powerpc/kernel/kvm.c | 92 ++-
arch/powerpc/kernel/kvm_emul.S | 93 ++-
2 files changed, 151 insertions(+), 34
ff-by: Scott Wood
---
arch/powerpc/kernel/kvm.c | 21 -
1 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index eb95a03..5e13500 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -30,6
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_e500.h |8 --
arch/powerpc/include/asm/kvm_host.h |2 -
arch/powerpc/include/asm/kvm_para.h | 28 +-
arch/powerpc/kernel/asm-offsets.c |9 ++
arch/powerpc/kernel/kvm.c | 201
negative.
Signed-off-by: Liu Yu
[scott: added dequeue in kvmppc_booke_irqprio_deliver, and dec stop-at-zero]
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/kvm_host.h |2 +-
arch/powerpc/include/asm/kvm_ppc.h | 11 +
arch/powerpc/kvm/book3s.c |8
arch/powerpc/kvm
Signed-off-by: Scott Wood
---
arch/powerpc/kvm/booke.c |4 ++--
arch/powerpc/kvm/e500.c |3 ---
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index ee45fa0..d967faf 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch
On 09/02/2011 10:12 AM, Alexander Graf wrote:
>
> Am 02.09.2011 um 01:08 schrieb Scott Wood :
>
>> Signed-off-by: Scott Wood
>
> Patch description missing.
It's not missing, it's just brief. :-)
I suppose you could add "The hardcoded behavior prevents
On 09/02/2011 08:53 AM, Alexander Graf wrote:
> On 08/27/2011 01:31 AM, Scott Wood wrote:
>> int_pending was only being lowered if a bit in pending_exceptions
>> was cleared during exception delivery -- but for interrupts, we clear
>> it during IACK/TSR emulation. Thi
On 09/02/2011 02:25 PM, Alexander Graf wrote:
>
> On 02.09.2011, at 20:17, Scott Wood wrote:
>
>> On 09/02/2011 08:53 AM, Alexander Graf wrote:
>>> On 08/27/2011 01:31 AM, Scott Wood wrote:
>>>> int_pending was only being lowered if a bit in pending_exceptio
On 09/02/2011 02:23 PM, Alexander Graf wrote:
>
> On 02.09.2011, at 20:14, Scott Wood wrote:
>
>> On 09/02/2011 10:12 AM, Alexander Graf wrote:
>>>
>>> Am 02.09.2011 um 01:08 schrieb Scott Wood :
>>>
>>>> Signed-off-by: Scott Wood
>>&
On 09/02/2011 02:25 PM, Alexander Graf wrote:
>
> On 02.09.2011, at 20:17, Scott Wood wrote:
>
>> On 09/02/2011 08:53 AM, Alexander Graf wrote:
>>> On 08/27/2011 01:31 AM, Scott Wood wrote:
>>>> int_pending was only being lowered if a bit in pending_exceptio
The hardcoded behavior prevents proper SMP support.
QEMU shall specify the vcpu's PIR as the vcpu id.
Signed-off-by: Scott Wood
---
v2: More detailed commit message.
arch/powerpc/kvm/booke.c |4 ++--
arch/powerpc/kvm/e500.c |3 ---
2 files changed, 2 insertions(+), 5 dele
On Wed, Sep 07, 2011 at 12:41:35PM +0200, Alexander Graf wrote:
> Yes, but why can't we do this in the vcpu thread's context so we only
> ever have a single instance accessing the vcpu struct? It makes a lot
> of things a lot easier.
Why? We don't do it for external interrupts. It would complic
On 09/05/2011 05:28 PM, Alexander Graf wrote:
>> +/*
>> + * SPRG4-7 are user-readable, so we can't keep these
>> + * consistent between the magic page and the real
>> + * registers. We provide space in case the guest
>> + * can deal with this.
>> + *
>> + * This also ap
On 09/08/2011 10:39 AM, Alexander Graf wrote:
>
> On 08.09.2011, at 17:34, Scott Wood wrote:
>
>> On Wed, Sep 07, 2011 at 12:41:35PM +0200, Alexander Graf wrote:
>>> Yes, but why can't we do this in the vcpu thread's context so we only
>>> ever have
On 09/05/2011 05:30 PM, Alexander Graf wrote:
>
> On 27.08.2011, at 01:31, Scott Wood wrote:
>
>> +#ifdef CONFIG_E500
>> +/*
>> + * Skip the overhead of HID0 accesses that KVM ignores --
>> + * just write MSR[WE].
>> + *
>> + * We
On 09/19/2011 04:23 AM, Alexander Graf wrote:
>
> On 15.09.2011, at 20:26, Scott Wood wrote:
>
>> However, I think it could work reasonably well to use this as the
>> backing store instead of vcpu->arch.sprg4-7. The guest would still see
>> inconsistency if it wri
On 09/19/2011 04:33 AM, Alexander Graf wrote:
>
> On 15.09.2011, at 23:36, Scott Wood wrote:
>
>> On 09/05/2011 05:30 PM, Alexander Graf wrote:
>>>
>>> On 27.08.2011, at 01:31, Scott Wood wrote:
>>>
>>>> +#ifdef CONFIG_E500
>>>
On 09/19/2011 04:32 AM, Alexander Graf wrote:
>
> On 15.09.2011, at 22:52, Scott Wood wrote:
>
>> On 09/08/2011 10:39 AM, Alexander Graf wrote:
>>>
>>> On 08.09.2011, at 17:34, Scott Wood wrote:
>>>
>>>> On Wed, Sep 07, 2011 at 12:41:35PM +0
On 09/19/2011 06:35 PM, Alexander Graf wrote:
> + /*
> + * e500 doesn't implement the lowest tsize bit,
> + * or 1K pages.
> + */
> + tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
> +
> +
On 09/24/2011 02:47 AM, Alexander Graf wrote:
>
> On 22.09.2011, at 08:50, Liu Yu-B13201 wrote:
>
>>
>>
>>> -Original Message-
>>> From: kvm-ppc-ow...@vger.kernel.org
>>> [mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Alexander Graf
>>> Sent: Tuesday, September 20, 2011 7:36 AM
>>>
On 09/24/2011 02:44 AM, Alexander Graf wrote:
> On 20.09.2011, at 19:54, Scott Wood wrote:
>> On 09/19/2011 06:35 PM, Alexander Graf wrote:
>>> + asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (psize));
>>> +
On 09/24/2011 02:27 AM, Alexander Graf wrote:
> I think I'm getting your point. So what we want is:
>
> in timer handler:
>
> set_bit(TSR_DIS, vcpu->arch.tsr);
> kvm_make_request(KVM_REQ_PPC_TSR_UPDATE, vcpu);
> kvm_vcpu_kick(vcpu);
>
> in vcpu entry code:
>
> if (vcpu->requests)
>
B13201; Wood Scott-B07421; kvm-ppc@vger.kernel.org
>>>> Subject: Re: [PATCH 5/5] KVM: PPC: booke: Improve timer register
>>>> emulation
>>>>
>>>>
>>>> On 27.09.2011, at 02:44, Scott Wood wrote:
>>>>
>>>>> On 09
tsize = min(__ilog2(psize) - 10, tsize);
Any reason for __ilog2() rather than ilog2()? Shouldn't make a
difference, just curious about avoiding the public interface.
Either way,
Acked-by: Scott Wood
-Scott
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