On 01/02/12 14:39, David Gibson wrote:
> On Tue, Jan 31, 2012 at 05:34:37PM +1100, Matt Evans wrote:
>> The generated DT is the bare minimum structure required for SPAPR (on which
>> subsequent patches for VIO, XICS, PCI etc. will build); root node, cpus,
>> memory.
>>
>> The DT contains CPU-speci
On Tue, Jan 31, 2012 at 05:34:37PM +1100, Matt Evans wrote:
> The generated DT is the bare minimum structure required for SPAPR (on which
> subsequent patches for VIO, XICS, PCI etc. will build); root node, cpus,
> memory.
>
> The DT contains CPU-specific configuration; a very simple 'cpu info' m
On 31 Jan 2012, at 18:59, Pekka Enberg wrote:
> On Tue, Jan 31, 2012 at 8:34 AM, Matt Evans wrote:
>> +static struct cpu_info cpu_power7_info = {
>> + "POWER7",
>> + power7_page_sizes_prop, sizeof(power7_page_sizes_prop),
>> + power7_segment_sizes_prop, sizeof(power7_segment_si
On Tue, Jan 31, 2012 at 8:34 AM, Matt Evans wrote:
> +static struct cpu_info cpu_power7_info = {
> + "POWER7",
> + power7_page_sizes_prop, sizeof(power7_page_sizes_prop),
> + power7_segment_sizes_prop, sizeof(power7_segment_sizes_prop),
> + 32, /* SLB size */
>
The generated DT is the bare minimum structure required for SPAPR (on which
subsequent patches for VIO, XICS, PCI etc. will build); root node, cpus, memory.
The DT contains CPU-specific configuration; a very simple 'cpu info' mechanism
is added to recognise/differentiate DT entries for POWER7 and
