On POWER, storage caching is usually configured via the MMU - attributes
such as cache-inhibited are stored in the TLB and the hashed page table.
This makes correctly performing cache inhibited IO accesses awkward when
the MMU is turned off (real mode). Some CPU models provide special
registers t
Am Tue, 21 Apr 2015 10:41:51 +1000
schrieb David Gibson :
> On POWER, storage caching is usually configured via the MMU - attributes
> such as cache-inhibited are stored in the TLB and the hashed page table.
>
> This makes correctly performing cache inhibited IO accesses awkward when
> the MMU is
On Tue, Apr 21, 2015 at 08:37:02AM +0200, Thomas Huth wrote:
> Am Tue, 21 Apr 2015 10:41:51 +1000
> schrieb David Gibson :
>
> > On POWER, storage caching is usually configured via the MMU - attributes
> > such as cache-inhibited are stored in the TLB and the hashed page table.
> >
> > This makes
Am Tue, 21 Apr 2015 16:51:21 +1000
schrieb David Gibson :
> On Tue, Apr 21, 2015 at 08:37:02AM +0200, Thomas Huth wrote:
> > Am Tue, 21 Apr 2015 10:41:51 +1000
> > schrieb David Gibson :
> >
> > > On POWER, storage caching is usually configured via the MMU - attributes
> > > such as cache-inhibit
On 04/21/2015 02:41 AM, David Gibson wrote:
On POWER, storage caching is usually configured via the MMU - attributes
such as cache-inhibited are stored in the TLB and the hashed page table.
This makes correctly performing cache inhibited IO accesses awkward when
the MMU is turned off (real mode)