On 04.02.2013, at 07:12, Bhushan Bharat-R65777 wrote:
Hi Alex/Scott,
Below is my understanding about the ONE_REG interface requirement for timer
registers.
Define the below 2 ONE_REG interface for TSR access:
KVM_REG_SET_TSR, // Set the specified bits in TSR
s/SET/OR/
Hi Alex/Scott,
Below is my understanding about the ONE_REG interface requirement for timer
registers.
Define the below 2 ONE_REG interface for TSR access:
KVM_REG_SET_TSR, // Set the specified bits in TSR
KVM_REG_CLEAR_TSR, // Clear the specified bits in TSR
QEMU will use the