Hello!
> I wonder if these patches would pave the way to support running GICv2
> guests on GICv3s without compat support?
Yes, it does. I haven't implemented GICv3 bit for this time, but - yes. And it
will be a very small
addition.
> Pavel, is this "broken" GIC you are talking about going to
On Mon, Jun 22, 2015 at 06:41:31PM +0800, Zhichao Huang wrote:
> The trapping code keeps track of the state of the debug registers,
> allowing for the switch code to implement a lazy switching strategy.
>
> Signed-off-by: Zhichao Huang
> ---
> arch/arm/include/asm/kvm_asm.h | 3 +++
> arch/arm
On Mon, Jun 22, 2015 at 06:41:32PM +0800, Zhichao Huang wrote:
> Implement switching of the debug registers. While the number
> of registers is massive, CPUs usually don't implement them all
> (A15 has 6 breakpoints and 4 watchpoints, which gives us a total
> of 22 registers "only").
>
> Notice th
On Mon, Jun 22, 2015 at 06:41:25PM +0800, Zhichao Huang wrote:
> pm_fake doesn't quite describe what the handler does (ignoring writes
> and returning 0 for reads).
>
> As we're about to use it (a lot) in a different context, rename it
> with a (admitedly cryptic) name that make sense for all user
On Mon, Jun 22, 2015 at 06:41:26PM +0800, Zhichao Huang wrote:
> Add #ifndef __ASSEMBLY__ in hw_breakpoint.h, in order to use
> the ARM_DSCR_MDBGEN macro from KVM assembly code.
>
> Signed-off-by: Zhichao Huang
> Reviewed-by: Alex Bennee
Acked-by: Christoffer Dall
_
On Mon, Jun 22, 2015 at 06:41:34PM +0800, Zhichao Huang wrote:
> Enable trapping of the debug registers, allowing guests to use
> the debug infrastructure.
>
> Signed-off-by: Zhichao Huang
> ---
> arch/arm/kvm/interrupts_head.S | 15 +--
> 1 file changed, 13 insertions(+), 2 deletion
On Mon, Jun 22, 2015 at 06:41:28PM +0800, Zhichao Huang wrote:
> We now have multiple tables for the various system registers
> we trap. Make sure we check the order of all of them, as it is
> critical that we get the order right (been there, done that...).
>
> Signed-off-by: Zhichao Huang
Revie
On Mon, Jun 22, 2015 at 06:41:30PM +0800, Zhichao Huang wrote:
> Add handlers for all the 64-bit debug registers.
>
> There is an overlap between 32 and 64bit registers. Make sure that
> 64-bit registers preceding 32-bit ones.
>
> Signed-off-by: Zhichao Huang
> ---
> arch/arm/kvm/coproc.c | 12
On Mon, Jun 22, 2015 at 06:41:33PM +0800, Zhichao Huang wrote:
> There are too many cp15 traps, so we don't reuse the cp15 trace event
> but add a new trace event to trace the access of debug registers.
>
> Signed-off-by: Zhichao Huang
Acked-by: Christoffer Dall
Hi Eric,
On 29/06/15 16:37, Eric Auger wrote:
> This patch adds compilation and link against irqchip.
>
> On ARM, irqchip routing is not really useful since there is
> a single irqchip. However main motivation behind using irqchip
> code is to enable MSI routing code. With the support of in-kerne
On 06/30/2015 03:39 PM, Andre Przywara wrote:
> Hi Eric,
>
> On 29/06/15 16:37, Eric Auger wrote:
>> This patch adds compilation and link against irqchip.
>>
>> On ARM, irqchip routing is not really useful since there is
>> a single irqchip. However main motivation behind using irqchip
>> code is
This fixes two instances where a pgprot_t is used as the operand
of a bitwise & operation. In order to comply with STRICT_MM_TYPECHECKS,
bitwise arithmetic on a pgprot_t should go via the pgprot_val()
accessor.
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Ard Biesheuvel
---
arch/arm/kvm/mmu.c
On Fri, Jun 26, 2015 at 02:16:15PM +0100, Andre Przywara wrote:
> Currently the ARM GIC checks the number of VCPUs against a fixed
> limit, which is GICv2 specific. Don't pretend we know better than the
> kernel and let's get rid of that explicit check.
> Instead be more relaxed about KVM_CREATE_VC
On Fri, Jun 26, 2015 at 02:16:18PM +0100, Andre Przywara wrote:
> Currently we unconditionally create a virtual GICv2 in the guest.
> Add a --irqchip= parameter to let the user specify a different GIC
> type for the guest, when omitting this parameter it still defaults to
> --irqchip=gicv2.
> For n
Hi,
On 30/06/15 17:09, Will Deacon wrote:
> On Fri, Jun 26, 2015 at 02:16:15PM +0100, Andre Przywara wrote:
>> Currently the ARM GIC checks the number of VCPUs against a fixed
>> limit, which is GICv2 specific. Don't pretend we know better than the
>> kernel and let's get rid of that explicit chec
On 30/06/15 17:13, Will Deacon wrote:
> On Fri, Jun 26, 2015 at 02:16:18PM +0100, Andre Przywara wrote:
>> Currently we unconditionally create a virtual GICv2 in the guest.
>> Add a --irqchip= parameter to let the user specify a different GIC
>> type for the guest, when omitting this parameter it s
On Tue, Jun 30, 2015 at 06:04:50PM +0200, Ard Biesheuvel wrote:
> This fixes two instances where a pgprot_t is used as the operand
> of a bitwise & operation. In order to comply with STRICT_MM_TYPECHECKS,
> bitwise arithmetic on a pgprot_t should go via the pgprot_val()
> accessor.
>
> Cc: kvmarm@
On Mon, Jun 08, 2015 at 06:04:01PM +0100, Marc Zyngier wrote:
> In order to be able to feed physical interrupts to a guest, we need
> to be able to establish the virtual-physical mapping between the two
> worlds.
>
> The mapping is kept in a rbtree, indexed by virtual interrupts.
how many of thes
On Mon, Jun 08, 2015 at 06:03:56PM +0100, Marc Zyngier wrote:
> As we now inject the timer interrupt when we're about to enter
> the guest, it makes a lot more sense to make sure this happens
> before the vgic code queues the pending interrupts.
>
> Otherwise, we get the interrupt on the following
On Mon, Jun 08, 2015 at 06:04:05PM +0100, Marc Zyngier wrote:
> So far, the only use of the HW interrupt facility is the timer,
> implying that the active state is context-switched for each vcpu,
> as the device is is shared across all vcpus.
>
> This does not work for a device that has been assig
On Mon, Jun 08, 2015 at 06:03:57PM +0100, Marc Zyngier wrote:
> As we're about to introduce some serious GIC-poking to the vgic code,
> it is important to make sure that we're going to poke the part of
> the GIC that belongs to the CPU we're about to run on (otherwise,
> we'd end up with some unexp
On Mon, Jun 08, 2015 at 06:04:00PM +0100, Marc Zyngier wrote:
> We only set the irq_queued flag for level interrupts, meaning
> that "!vgic_irq_is_queued(vcpu, irq)" is a good enough predicate
> for all interrupts.
>
> This will allow us to inject edge HW interrupts, for which the
> state ACTIVE+P
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