Hi all
I want to try kvm arm, but i cannot find a board which supports arm
hardware-assist visualization. I knows there are some boards like arndale
supports it, but i cannot get it. So i am wondering if there are some phones
which uses qualcomm or nivida's cpu also supports it.
thanksyoung
This includes trace points for:
kvm_arch_setup_guest_debug
kvm_arch_clear_guest_debug
I've also added some generic register setting trace events and also a
trace point to dump the array of hardware registers.
Signed-off-by: Alex Bennée
---
v3
- add trace event for debug access.
- remove
This commit defines the API headers for guest debugging. There are two
architecture specific debug structures:
- kvm_guest_debug_arch, allows us to pass in HW debug registers
- kvm_debug_exit_arch, signals exception and possible faulting address
The type of debugging being used is controlled
This introduces a level of indirection for the debug registers. Instead
of using the sys_regs[] directly we store registers in a structure in
the vcpu. The new kvm_arm_reset_debug_ptr() sets the debug ptr to the
guest context.
This also entails updating the sys_regs code to access this new
structu
Bring into line with the comments for the other structures and their
KVM_EXIT_* cases. Also update api.txt to reflect use in kvm_run
documentation.
Signed-off-by: Alex Bennée
Reviewed-by: David Hildenbrand
Reviewed-by: Andrew Jones
Acked-by: Christoffer Dall
---
v2
- add comments for other
This adds support for userspace to control the HW debug registers for
guest debug. In the debug ioctl we copy an IMPDEF registers into a new
register set called host_debug_state.
We use the recently introduced vcpu parameter debug_ptr to select which
register set is copied into the real registers
This adds support for SW breakpoints inserted by userspace.
We do this by trapping all guest software debug exceptions to the
hypervisor (MDCR_EL2.TDE). The exit handler sets an exit reason of
KVM_EXIT_DEBUG with the kvm_debug_exit_arch structure holding the
exception syndrome information.
It wil
This adds support for single-stepping the guest. To do this we need to
manipulate the guests PSTATE.SS and MDSCR_EL1.SS bits to trigger
stepping. We take care to preserve MDSCR_EL1 and trap access to it to
ensure we don't affect the apparent state of the guest.
As we have to enable trapping of all
This is a pre-cursor to sharing the code with the guest debug support.
This replaces the big macro that fishes data out of a fixed location
with a more general helper macro to restore a set of debug registers. It
uses macro substitution so it can be re-used for debug control and value
registers. It
This is a precursor for later patches which will need to do more to
setup debug state before entering the hyp.S switch code. The existing
functionality for setting mdcr_el2 has been moved out of hyp.S and now
uses the value kept in vcpu->arch.mdcr_el2.
As the assembler used to previously mask and
Finally advertise the KVM capability for SET_GUEST_DEBUG. Once arm
support is added this check can be moved to the common
kvm_vm_ioctl_check_extension() code.
Signed-off-by: Alex Bennée
Acked-by: Christoffer Dall
---
v3:
- separated capability check from previous patches
- moved into arm64 s
Here is V7 of the KVM Guest Debug support for arm64.
The fixes are fairly minor aside from the re-factoring of sys_regs.c
to have individual trap functions for each debug register. There is a
lot of boiler plate but it does make the ugliness of the previous
offset hacks go away.
On top of that I'
This commit adds a stub function to support the KVM_SET_GUEST_DEBUG
ioctl. Any unsupported flag will return -EINVAL. For now, only
KVM_GUESTDBG_ENABLE is supported, although it won't have any effects.
Signed-off-by: Alex Bennée .
Reviewed-by: Christoffer Dall
---
v2
- simplified form of the io
On 01/07/15 12:58, Christoffer Dall wrote:
> On Wed, Jul 01, 2015 at 10:17:52AM +0100, Marc Zyngier wrote:
>> On 30/06/15 21:19, Christoffer Dall wrote:
>>> On Mon, Jun 08, 2015 at 06:04:00PM +0100, Marc Zyngier wrote:
We only set the irq_queued flag for level interrupts, meaning
that "!v
On 1 July 2015 at 14:28, Catalin Marinas wrote:
> On Wed, Jul 01, 2015 at 02:18:31PM +0100, Catalin Marinas wrote:
>> On Wed, Jul 01, 2015 at 02:08:31PM +0200, Christoffer Dall wrote:
>> > diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
>> > index 2de9d2e..0eeb4f09 100644
>>
On Wed, Jun 24, 2015 at 05:04:12PM -0700, Mario Smarduch wrote:
> After enhancing arm64 FP/SIMD exit handling, ARMv7 VFP exit branch is moved
> to guest trap handling. This allows us to keep exit handling flow between both
> architectures consistent.
>
> Signed-off-by: Mario Smarduch
> ---
> arc
On Wed, Jun 24, 2015 at 05:04:11PM -0700, Mario Smarduch wrote:
> This patch only saves and restores FP/SIMD registers on Guest access. To do
> this cptr_el2 FP/SIMD trap is set on Guest entry and later checked on exit.
> lmbench, hackbench show significant improvements, for 30-50% exits FP/SIMD
>
On Wed, Jul 01, 2015 at 02:18:31PM +0100, Catalin Marinas wrote:
> On Wed, Jul 01, 2015 at 02:08:31PM +0200, Christoffer Dall wrote:
> > diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> > index 2de9d2e..0eeb4f09 100644
> > --- a/arch/arm64/mm/hugetlbpage.c
> > +++ b/arch/arm
On Wed, Jul 01, 2015 at 02:08:31PM +0200, Christoffer Dall wrote:
> The current pmd_huge() and pud_huge() functions simply check if the table
> bit is not set and reports the entries as huge in that case. This is
> counter-intuitive as a clear pmd/pud cannot also be a huge pmd/pud, and
> it is inc
On 01/07/15 13:08, Christoffer Dall wrote:
> The current pmd_huge() and pud_huge() functions simply check if the table
> bit is not set and reports the entries as huge in that case. This is
> counter-intuitive as a clear pmd/pud cannot also be a huge pmd/pud, and
> it is inconsistent with at least
On Wed, Jul 01, 2015 at 01:24:34PM +0100, Steve Capper wrote:
> On 1 July 2015 at 13:08, Christoffer Dall wrote:
> > The current pmd_huge() and pud_huge() functions simply check if the table
> > bit is not set and reports the entries as huge in that case. This is
> > counter-intuitive as a clear
On 1 July 2015 at 13:08, Christoffer Dall wrote:
> The current pmd_huge() and pud_huge() functions simply check if the table
> bit is not set and reports the entries as huge in that case. This is
> counter-intuitive as a clear pmd/pud cannot also be a huge pmd/pud, and
> it is inconsistent with a
The current pmd_huge() and pud_huge() functions simply check if the table
bit is not set and reports the entries as huge in that case. This is
counter-intuitive as a clear pmd/pud cannot also be a huge pmd/pud, and
it is inconsistent with at least arm and x86.
To prevent others from making the sa
On Wed, Jul 01, 2015 at 10:17:52AM +0100, Marc Zyngier wrote:
> On 30/06/15 21:19, Christoffer Dall wrote:
> > On Mon, Jun 08, 2015 at 06:04:00PM +0100, Marc Zyngier wrote:
> >> We only set the irq_queued flag for level interrupts, meaning
> >> that "!vgic_irq_is_queued(vcpu, irq)" is a good enough
On Wed, Jul 01, 2015 at 11:20:45AM +0100, Marc Zyngier wrote:
> On 30/06/15 21:19, Christoffer Dall wrote:
> > On Mon, Jun 08, 2015 at 06:04:01PM +0100, Marc Zyngier wrote:
> >> In order to be able to feed physical interrupts to a guest, we need
> >> to be able to establish the virtual-physical map
On 30/06/15 18:03, Catalin Marinas wrote:
> On Tue, Jun 30, 2015 at 06:04:50PM +0200, Ard Biesheuvel wrote:
>> This fixes two instances where a pgprot_t is used as the operand
>> of a bitwise & operation. In order to comply with STRICT_MM_TYPECHECKS,
>> bitwise arithmetic on a pgprot_t should go vi
On 30/06/15 21:19, Christoffer Dall wrote:
> On Mon, Jun 08, 2015 at 06:04:01PM +0100, Marc Zyngier wrote:
>> In order to be able to feed physical interrupts to a guest, we need
>> to be able to establish the virtual-physical mapping between the two
>> worlds.
>>
>> The mapping is kept in a rbtree,
On Wed, Jun 24, 2015 at 05:04:10PM -0700, Mario Smarduch wrote:
> Currently we save/restore fp/simd on each exit. Fist patch optimizes arm64
> save/restore, we only do so on Guest access. hackbench and
> several lmbench tests show anywhere from 30% to above 50% optimzation
> achieved.
>
> In seco
On 30/06/15 21:19, Christoffer Dall wrote:
> On Mon, Jun 08, 2015 at 06:04:00PM +0100, Marc Zyngier wrote:
>> We only set the irq_queued flag for level interrupts, meaning
>> that "!vgic_irq_is_queued(vcpu, irq)" is a good enough predicate
>> for all interrupts.
>>
>> This will allow us to inject e
On Wed, Jul 01, 2015 at 03:09:35PM +0800, zichao wrote:
>
>
> On June 30, 2015 3:43:34 AM GMT+08:00, Christoffer Dall
> wrote:
> >On Mon, Jun 22, 2015 at 06:41:27PM +0800, Zhichao Huang wrote:
> >> As we're about to trap a bunch of CP14 registers, let's rework
> >> the CP15 handling so it can b
On Wed, Jul 01, 2015 at 03:04:00PM +0800, zichao wrote:
>
>
> On June 29, 2015 11:49:53 PM GMT+08:00, Christoffer Dall
> wrote:
> >On Mon, Jun 22, 2015 at 06:41:24PM +0800, Zhichao Huang wrote:
> >> Hardware debugging in guests is not intercepted currently, it means
> >> that a malicious guest
On Wed, Jul 01, 2015 at 09:26:59AM +0100, Marc Zyngier wrote:
> On 30/06/15 21:19, Christoffer Dall wrote:
> > On Mon, Jun 08, 2015 at 06:04:05PM +0100, Marc Zyngier wrote:
> >> So far, the only use of the HW interrupt facility is the timer,
> >> implying that the active state is context-switched f
On 30/06/15 21:19, Christoffer Dall wrote:
> On Mon, Jun 08, 2015 at 06:04:05PM +0100, Marc Zyngier wrote:
>> So far, the only use of the HW interrupt facility is the timer,
>> implying that the active state is context-switched for each vcpu,
>> as the device is is shared across all vcpus.
>>
>> Th
On June 30, 2015 9:20:29 PM GMT+08:00, Christoffer Dall
wrote:
>On Mon, Jun 22, 2015 at 06:41:30PM +0800, Zhichao Huang wrote:
>> Add handlers for all the 64-bit debug registers.
>>
>> There is an overlap between 32 and 64bit registers. Make sure that
>> 64-bit registers preceding 32-bit ones.
On June 30, 2015 5:16:41 AM GMT+08:00, Christoffer Dall
wrote:
>On Mon, Jun 22, 2015 at 06:41:29PM +0800, Zhichao Huang wrote:
>> Add handlers for all the 32-bit debug registers.
>>
>> Signed-off-by: Zhichao Huang
>> ---
>> arch/arm/include/asm/kvm_asm.h | 12
>> arch/arm/include/asm/
On June 30, 2015 3:43:34 AM GMT+08:00, Christoffer Dall
wrote:
>On Mon, Jun 22, 2015 at 06:41:27PM +0800, Zhichao Huang wrote:
>> As we're about to trap a bunch of CP14 registers, let's rework
>> the CP15 handling so it can be generalized and work with multiple
>> tables.
>>
>> Signed-off-by:
On June 29, 2015 11:49:53 PM GMT+08:00, Christoffer Dall
wrote:
>On Mon, Jun 22, 2015 at 06:41:24PM +0800, Zhichao Huang wrote:
>> Hardware debugging in guests is not intercepted currently, it means
>> that a malicious guest can bring down the entire machine by writing
>> to the debug registers
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