Re: [PATCH v3 3/4] irqchip: GIC: Convert to EOImode == 1

Hi Thomas, On 25/08/15 16:46, Thomas Gleixner wrote: > On Tue, 25 Aug 2015, Marc Zyngier wrote: >> +static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; >> + >> #ifndef MAX_GIC_NR >> #define MAX_GIC_NR 1 >> #endif >> @@ -137,6 +140,14 @@ static inline unsigned int gic_irq(struc

Re: [PATCH v3 3/4] irqchip: GIC: Convert to EOImode == 1

On Tue, 25 Aug 2015, Marc Zyngier wrote: > +static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; > + > #ifndef MAX_GIC_NR > #define MAX_GIC_NR 1 > #endif > @@ -137,6 +140,14 @@ static inline unsigned int gic_irq(struct irq_data *d) > return d->hwirq; > } > > +static in

Re: [PATCH v2 12/15] KVM: arm64: sync LPI configuration and pending tables

Hi Eric, On 14/08/15 13:35, Eric Auger wrote: > On 08/14/2015 01:58 PM, Eric Auger wrote: >> On 07/10/2015 04:21 PM, Andre Przywara wrote: >>> The LPI configuration and pending tables of the GICv3 LPIs are held >>> in tables in (guest) memory. To achieve reasonable performance, we >>> cache this d

Re: [PATCH v2 12/15] KVM: arm64: sync LPI configuration and pending tables

Hi Eric, On 14/08/15 12:58, Eric Auger wrote: > On 07/10/2015 04:21 PM, Andre Przywara wrote: >> The LPI configuration and pending tables of the GICv3 LPIs are held >> in tables in (guest) memory. To achieve reasonable performance, we >> cache this data in our own data structures, so we need to sy

Re: [PATCH v2 11/15] KVM: arm64: handle pending bit for LPIs in ITS emulation

Hi Eric, On 14/08/15 12:58, Eric Auger wrote: > On 07/10/2015 04:21 PM, Andre Przywara wrote: >> As the actual LPI number in a guest can be quite high, but is mostly >> assigned using a very sparse allocation scheme, bitmaps and arrays >> for storing the virtual interrupt status are a waste of mem

[PATCH v3 4/4] irqchip: GIC: Don't deactivate interrupts forwarded to a guest

Commit 0a4377de3056 ("genirq: Introduce irq_set_vcpu_affinity() to target an interrupt to a VCPU") added just what we needed at the lowest level to allow an interrupt to be deactivated by a guest. When such a request reaches the GIC, it knows it doesn't need to perform the deactivation anymore, an

[PATCH v3 0/4] irqchip: GICv2/v3: Add support for irq_vcpu_affinity

The GICv2 and GICv3 architectures allow an active physical interrupt to be forwarded to a guest, and the guest to indirectly perform the deactivation of the interrupt by performing an EOI on the virtual interrupt (see for example the GICv2 spec, 3.2.1). This allows some substantial performance imp

[PATCH v3 2/4] irqchip: GICv3: Don't deactivate interrupts forwarded to a guest

Commit 0a4377de3056 ("genirq: Introduce irq_set_vcpu_affinity() to target an interrupt to a VCPU") added just what we needed at the lowest level to allow an interrupt to be deactivated by a guest. When such a request reaches the GIC, it knows it doesn't need to perform the deactivation anymore, an

[PATCH v3 1/4] irqchip: GICv3: Convert to EOImode == 1

So far, GICv3 has been used in with EOImode == 0. The effect of this mode is to perform the priority drop and the deactivation of the interrupt at the same time. While this works perfectly for Linux (we only have a single priority), it causes issues when an interrupt is forwarded to a guest, and w

[PATCH v3 3/4] irqchip: GIC: Convert to EOImode == 1

So far, GICv2 has been used with EOImode == 0. The effect of this mode is to perform the priority drop and the deactivation of the interrupt at the same time. While this works perfectly for Linux (we only have a single priority), it causes issues when an interrupt is forwarded to a guest, and when

RE: KVM Live migration with GICv3

Hello! Where are you? I'd like to take a look at your code. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia > -Original Message- > From: Vijay Kilari [mailto:vijay.kil...@gmail.com] > Sent: Tuesday, August 11, 2015 6:16 PM > To: Pavel Fedin > Cc: kvm

Re: [PATCH v2 10/15] KVM: arm64: add data structures to model ITS interrupt translation

Hi Eric, On 13/08/15 16:46, Eric Auger wrote: > > On 07/10/2015 04:21 PM, Andre Przywara wrote: >> The GICv3 Interrupt Translation Service (ITS) uses tables in memory >> to allow a sophisticated interrupt routing. It features device tables, >> an interrupt table per device and a table connecting

Re: [PATCH v2 09/15] KVM: arm64: implement basic ITS register handlers

Hi Eric, >> diff --git a/virt/kvm/arm/its-emul.c b/virt/kvm/arm/its-emul.c >> index 659dd39..b498f06 100644 >> --- a/virt/kvm/arm/its-emul.c >> +++ b/virt/kvm/arm/its-emul.c >> @@ -32,10 +32,62 @@ >> #include "vgic.h" >> #include "its-emul.h" >> >> +#define BASER_BASE_ADDRESS(x) ((x) & 0xf

Re: [PATCH v2 08/15] KVM: arm64: introduce ITS emulation file with stub functions

Salut Eric, >> diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c >> index 5269ad1..f5865e7 100644 >> --- a/virt/kvm/arm/vgic-v3-emul.c >> +++ b/virt/kvm/arm/vgic-v3-emul.c >> @@ -48,6 +48,7 @@ >> #include >> >> #include "vgic.h" >> +#include "its-emul.h" >> >> st