RE: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

Hello Andre and others! How are things going? I see the last message in thread something like 1 month old, then silence... Our project relies on this feature, any assistance needed? Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia

RE: [PATCH 1/3] arm/arm64: KVM: vgic: Check for !irqchip_in_kernel() when mapping resources

Hello! > Until b26e5fdac43c ("arm/arm64: KVM: introduce per-VM ops"), > kvm_vgic_map_resources() used to include a check on irqchip_in_kernel(), > and vgic_v2_map_resources() still has it. I'm back from vacation and very glad to see myself being useful :) What's with the rest of that patch

Re: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

Hi Pavel, On 24/09/15 12:18, Pavel Fedin wrote: > Hello Andre and others! > > How are things going? I see the last message in thread something like 1 > month old, then silence... > Our project relies on this feature, any assistance needed? I am about to make it work on top of Christoffer's

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RE: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

Hello! > The only thing that is pure 64-bit is the MRS/MSR _instruction_ in > Aarch64, which always takes a x register. > So can you model the register size according to the spec and allow > 32-bit accesses from userland? I would like to complete the rework and respin v4, but this is, i guess,

[PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Add a helper for CP15 registers reset to UNKNOWN. Signed-off-by: Shannon

[PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing

When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 4

[PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c

[PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register

The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shannon Zhao ---

[PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c

[PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c

[PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers

We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59

[PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu

Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to ARMv8 spec, the PMU

[PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in KVM, directly use raw event type to create a

[PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao ---

[PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 18 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 91cf535..4da7f6c 100644

[PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device

Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/uapi/asm/kvm.h | 3 + include/linux/kvm_host.h

[PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++

[PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR, call

[PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29 + 1 file changed, 25 insertions(+), 4

[PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h

To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45

[PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 33 ++--- 1 file

[PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for the selected event