[PATCH v3 4/4] KVM: arm/arm64: implement kvm_arm_[halt,resume]_guest

We introduce kvm_arm_halt_guest and resume functions. They will be used for IRQ forward state change. Halt is synchronous and prevents the guest from being re-entered. We use the same mechanism put in place for PSCI former pause, now renamed power_off. A new flag is introduced in arch vcpu state,

[PATCH v3 1/4] KVM: arm/arm64: rename pause into power_off

The kvm_vcpu_arch pause field is renamed into power_off to prepare for the introduction of a new pause field. Also vcpu_pause is renamed into vcpu_sleep since we will sleep until both power_off and pause are false. Signed-off-by: Eric Auger Reviewed-by: Christoffer Dall

[PATCH v3 0/4] KVM: arm/arm64: guest synchronous halt/resume

This series introduces the capability to synchronously exit the guest and prevent it from being re-entered. This modality will be used by IRQ forwarding series when changing the state of the IRQ. Former pause flag used when starting the vcpu in KVM_ARM_VCPU_POWER_OFF state, in PSCI calls and in

[PATCH v3 2/4] KVM: arm/arm64: check power_off in kvm_arch_vcpu_runnable

kvm_arch_vcpu_runnable now also checks whether the power_off flag is set. Signed-off-by: Eric Auger Reviewed-by: Christoffer Dall --- arch/arm/kvm/arm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/kvm/arm.c

Re: [RFC 0/2] VFIO: Add virtual MSI doorbell support.

On Tue, Sep 22, 2015 at 11:09:14PM +0100, Marc Zyngier wrote: > On Tue, 4 Aug 2015 06:52:01 +0100 > Bhushan Bharat wrote: > > > > > > > > -Original Message- > > > From: Pranavkumar Sawargaonkar [mailto:pranavku...@linaro.org] > > > Sent: Tuesday, August

Re: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

On 24/09/15 13:08, Pavel Fedin wrote: > Hello! > >> The only thing that is pure 64-bit is the MRS/MSR _instruction_ in >> Aarch64, which always takes a x register. >> So can you model the register size according to the spec and allow >> 32-bit accesses from userland? > > I would like to

Re: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

On 25 September 2015 at 15:27, Andre Przywara wrote: > On 24/09/15 13:08, Pavel Fedin wrote: >> Hello! >> >>> The only thing that is pure 64-bit is the MRS/MSR _instruction_ in >>> Aarch64, which always takes a x register. >>> So can you model the register size according

Re: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

On Fri, 25 Sep 2015 15:33:44 -0700 Peter Maydell wrote: > On 25 September 2015 at 15:27, Andre Przywara wrote: > > On 24/09/15 13:08, Pavel Fedin wrote: > >> Hello! > >> > >>> The only thing that is pure 64-bit is the MRS/MSR _instruction_ in >