Now that the arm64 rewrite is in mainline, I've taken a stab at fixing
the 32bit code the same way. This is fairly straightforward (once
you've been through it once...), with a few patches that adapt the
code to be similar to the 64bit version.
Note that the timer and GIC code should be made
This patch shouldn't exist, as we should be able to reuse the
arm64 version for free. I'll get there eventually, but in the
meantime I need a timer ticking.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/Makefile | 1 +
arch/arm/kvm/hyp/hyp.h | 8 +
Now that we've unified the way we refer to the HYP text between
arm and arm64, drop __kvm_hyp_code_start/end, and just use the
__hyp_text_start/end symbols.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_asm.h | 3 ---
arch/arm/kvm/arm.c | 2 +-
Continuing our rework of the CPU context, we now move the CP15
array into the CPU context structure. As this causes quite a bit
of churn, we introduce the vcpu_cp15() macro that abstract the
location of the actual array. This will probably help next time
we have to revisit that code.
Having u64 as the kvm_call_hyp return type is problematic, as
it forces all kind of tricks for the return values from HYP
to be promoted to 64bit (LE has the LSB in r0, and BE has them
in r1).
Since the only user of the return value is perfectly happy with
a 32bit value, let's make kvm_call_hyp
This is almost a copy/paste of the existing version, with a couple
of subtle differences:
- Only write to FPEXC once on the save path
- Add an isb when enabling VFP access
The patch also defines a few sysreg accessors and a __vfp_enabled
predicate that test the VFP trapping state.
Signed-off-by:
Add the very minimal piece of code that is now required to jump
into the guest (and return from it). This code is only concerned
with save/restoring the USR registers (r0-r12+lr for the guest,
r4-r12+lr for the host), as everything else is dealt with in C
(VFP is another matter though).
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_asm.h | 2 ++
arch/arm/include/asm/kvm_host.h | 1 +
arch/arm/kvm/hyp/Makefile | 1 +
arch/arm/kvm/hyp/hyp.h | 2 ++
arch/arm/kvm/hyp/s2-setup.c | 34 ++
Since we don't have much assembler left, most of the KVM stuff
in asm-offsets.c is now superfluous. Let's get rid of it.
Signed-off-by: Marc Zyngier
---
arch/arm/kernel/asm-offsets.c | 30 --
1 file changed, 30 deletions(-)
diff --git
This field was never populated, and the panic code already
does something similar. Delete the related code.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_emulate.h | 5 -
arch/arm/include/asm/kvm_host.h| 1 -
arch/arm/kernel/asm-offsets.c | 1 -
Similar to the arm64 version, add the code that deals with VFP traps,
re-enabling VFP, save/restoring the registers and resuming the guest.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/entry.S | 31 +++
1 file changed, 31 insertions(+)
diff
This part is almost entierely borrowed from the existing code, just
slightly simplifying the HYP function call (as we now save SPSR_hyp
in the world switch).
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/Makefile| 1 +
arch/arm/kvm/hyp/hyp-entry.S | 157
Now that the old code is long gone, we can remove all the weak
attributes, as there is only one version of the code.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/hyp-entry.S | 4 +---
arch/arm/kvm/hyp/switch.c| 2 +-
arch/arm/kvm/hyp/tlb.c | 6 +++---
3 files
Instead of spinning forever, let's "properly" handle any unexpected
exception ("properly" meaning "print a spat on the console and die").
This has proved useful quite a few times...
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/hyp-entry.S | 28
I have no idea what these were for - probably a leftover from an
early implementation. Good bye!
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_asm.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/include/asm/kvm_asm.h
This patch shouldn't exist, as we should be able to reuse the
arm64 version for free. I'll get there eventually, but in the
meantime I need an interrupt controller.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/Makefile | 1 +
arch/arm/kvm/hyp/hyp.h| 3 ++
Just like on arm64, having the CP15 registers expressed as a set
of #defines has been very conflict-prone. Let's turn it into an
enum, which should make it more manageable.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_asm.h | 33
In order to be able to spread the HYP code into multiple compilation
units, adopt a layout similar to that of arm64:
- the HYP text is emited in its own section (.hyp.text)
- two linker generated symbols are use to identify the boundaries
of that section
No functionnal change.
Signed-off-by:
Continuing our rework of the CPU context, we now move the GP
registers into the CPU context structure.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_emulate.h | 8
arch/arm/include/asm/kvm_host.h| 3 +--
arch/arm/kernel/asm-offsets.c | 18
In order to turn the WS code into something that looks a bit
more like the arm64 version, move the VFP registers into a
CPU context container for both the host and the guest.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_host.h | 11 +++
In order to expose the various HYP services that are private to
the hypervisor, add a new hyp.h file.
So far, it only contains mundane things such as section annotation
and VA manipulation.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/hyp.h | 30
In order to move system register (CP15, mostly) access to C code,
add a few macros to facilitate this, and minimize the difference
between 32 and 64bit CP15 registers.
This will get heavily used in the following patches.
Signed-off-by: Marc Zyngier
---
Banked registers are one of the many perks of the 32bit architecture,
and the world switch needs to cope with it.
This requires some "special" accessors, as these are not accessed
using a standard coprocessor instruction.
Signed-off-by: Marc Zyngier
---
From: Shannon Zhao
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao
Reviewed-by: Andrew Jones
From: Shannon Zhao
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.
Signed-off-by: Shannon Zhao
Reviewed-by: Andrew Jones
From: Shannon Zhao
When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when the perf event overflows, set the
corresponding bit of guest PMOVSSET register. If this counter is enabled
and its interrupt is enabled as well,
From: Shannon Zhao
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.
Signed-off-by: Shannon Zhao
Reviewed-by: Andrew Jones
---
From: Shannon Zhao
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao
---
arch/arm64/kvm/sys_regs.c | 29
From: Shannon Zhao
This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get
From: Shannon Zhao
This register resets as unknown in 64bit mode while it resets as zero
in 32bit mode. Here we choose to reset it as zero for consistency.
PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers
From: Shannon Zhao
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel
Signed-off-by: Shannon Zhao
Acked-by: Marc Zyngier
From: Shannon Zhao
To configure the virtual PMUv3 overflow interrupt number, we use the
vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group.
After configuring the PMUv3, call the vcpu ioctl with attribute
From: Shannon Zhao
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.
When writing non-zero value to PMOVSSET, the counter and its interrupt
is enabled, kick
From: Shannon Zhao
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.
The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking
From: Shannon Zhao
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.
Signed-off-by: Shannon Zhao
Reviewed-by: Andrew Jones
From: Shannon Zhao
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for
From: Shannon Zhao
When KVM frees VCPU, it needs to free the perf_event of PMU.
Signed-off-by: Shannon Zhao
Reviewed-by: Marc Zyngier
Reviewed-by: Andrew Jones
---
arch/arm/kvm/arm.c| 1 +
On Wed, Feb 03, 2016 at 06:00:12PM +, Marc Zyngier wrote:
> The fault decoding process (including computing the IPA in the case
> of a permission fault) would be much better done in C code, as we
> have a reasonable infrastructure to deal with the VHE/non-VHE
> differences.
>
> Let's move the
On Wed, Feb 03, 2016 at 06:00:13PM +, Marc Zyngier wrote:
> When the kernel is running in HYP (with VHE), it is necessary to
> include EL2 events if the user requests counting kernel or
> hypervisor events.
>
> Signed-off-by: Marc Zyngier
> ---
>
On Wed, Feb 03, 2016 at 06:00:16PM +, Marc Zyngier wrote:
> Having both VHE and non-VHE capable CPUs in the same system
> is likely to be a recipe for disaster.
>
> If the boot CPU has VHE, but a secondary is not, we won't be
> able to downgrade and run the kernel at EL1. Add CPU hotplug
> to
On Wed, Feb 03, 2016 at 06:00:15PM +, Marc Zyngier wrote:
> With ARMv8.1 VHE, the architecture is able to (almost) transparently
> run the kernel at EL2, despite being written for EL1.
>
> This patch takes care of the "almost" part, mostly preventing the kernel
> from dropping from EL2 to
On Wed, Feb 03, 2016 at 05:59:53PM +, Marc Zyngier wrote:
> ARMv8.1 comes with the "Virtualization Host Extension" (VHE for
> short), which enables simpler support of Type-2 hypervisors.
>
> This extension allows the kernel to directly run at EL2, and
> significantly reduces the number of
Hi,
I'm involved in planning a project for which there is a requirement for PCIe
passthrough in KVM on ARMv8. We have no hardware to test on at the moment.
I understand that virtualisation support for ARM is quite young, and it seems
like support is trickling in at the moment for this sort of
On Thu, Feb 04, 2016 at 01:18:38PM +0100, Alexander Gordeev wrote:
> On Fri, Jan 15, 2016 at 04:32:11PM +0100, Andrew Jones wrote:
> > > +struct pci_testdev_ops {
> > > + u8 (*read8)(const volatile void *addr);
> > > + u16 (*read16)(const volatile void *addr);
> > > + u32 (*read32)(const volatile
Hi Edward,
On 02/04/2016 05:53 PM, Edward Cragg wrote:
> Hi,
>
> I'm involved in planning a project for which there is a requirement for PCIe
> passthrough in KVM on ARMv8. We have no hardware to test on at the moment.
>
> I understand that virtualisation support for ARM is quite young, and it
Hi Drew,
On 04/02/16 18:38, Andrew Jones wrote:
>
> Hi Marc and Andre,
>
> I completely understand why reset_mpidr() limits Aff0 to 16, thanks
> to Andre's nice comment about ICC_SGIxR. Now, here's my question;
> it seems that the Cortex-A{53,57,72} manuals want to further limit
> Aff0 to 4,
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