Re: [PATCH v3 53/55] KVM: arm/arm64: vgic-new: Wire up irqfd injection

On Fri, May 06, 2016 at 11:46:06AM +0100, Andre Przywara wrote: > Connect to the new VGIC to the irqfd framework, so that we can > inject IRQs. > GSI routing and MSI routing is not yet implemented. > > Signed-off-by: Andre Przywara > --- > virt/kvm/arm/vgic/vgic-irqfd.c

Re: [PATCH] fixup! vgic-new: make vgic_register_redist_iodevs more readable

On Thu, May 12, 2016 at 01:44:28PM +0100, Andre Przywara wrote: > Signed-off-by: Andre Przywara > --- > virt/kvm/arm/vgic/vgic-mmio-v3.c | 42 > > 1 file changed, 21 insertions(+), 21 deletions(-) > > diff --git

Re: [PATCH v3 54/55] KVM: arm/arm64: vgic-new: implement mapped IRQ handling

On Fri, May 06, 2016 at 11:46:07AM +0100, Andre Przywara wrote: > We now store the mapped hardware IRQ number in our struct, so we > don't need the irq_phys_map for the new VGIC. > Implement the hardware IRQ mapping on top of the reworked arch > timer interface. > > Signed-off-by: Andre Przywara

Re: [PATCH v2] KVM: arm/arm64: vgic-new: fix overlap check for device addresses

On Tue, May 10, 2016 at 06:18:46PM +0100, Andre Przywara wrote: > When userland sets the base addresses for the GIC register frames, > the kernel tries to make sure that the regions for the distributor and > the one for the CPU interface or the redistributors do not overlap. > Currently this check

Re: [PATCH v3 51/55] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources

On Fri, May 06, 2016 at 11:46:04AM +0100, Andre Przywara wrote: > From: Eric Auger > > map_resources is the last initialization step. It is executed on > 1st VCPU run. At that stage the code checks the userspace has provided > the base addresses for the relevant VGIC

Re: [PATCH v3 52/55] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable

On Fri, May 06, 2016 at 11:46:05AM +0100, Andre Przywara wrote: > From: Eric Auger > > Enable the VGIC operation by properly initialising the registers > in the hypervisor GIC interface. > > Signed-off-by: Eric Auger > Signed-off-by: Andre Przywara

Re: [PATCH v3 50/55] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init

On Fri, May 06, 2016 at 11:46:03AM +0100, Andre Przywara wrote: > From: Eric Auger > > This patch allocates and initializes the data structures used > to model the vgic distributor and virtual cpu interfaces. At that > stage the number of IRQs and number of virtual CPUs is

Re: [PATCH v3 45/55] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers

Hi, On 12/05/16 19:41, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:58AM +0100, Andre Przywara wrote: >> Userland may want to save and restore the state of the in-kernel VGIC, >> so we provide the code which takes a userland request and translate >> that into calls to our MMIO

Re: [PATCH v2] KVM: arm/arm64: vgic-new: Switch to firmware-independent probing

On Tue, May 10, 2016 at 09:46:23AM +0100, Marc Zyngier wrote: > As we did for the legacy code, switch the new VGIC implementation > the firmware-independent probing, giving us ACPI support for free. > > Signed-off-by: Marc Zyngier So just remembered you wrote this after

Re: [PATCH v3 48/55] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init

On Fri, May 06, 2016 at 11:46:01AM +0100, Andre Przywara wrote: > From: Eric Auger > > Implements kvm_vgic_hyp_init and vgic_probe function. > > The vgic_global struct is enriched with new fields populated > by those functions. > > Signed-off-by: Eric Auger

Re: [PATCH v3 47/55] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access

Hi, On 12/05/16 19:47, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:46:00AM +0100, Andre Przywara wrote: >> Using the VMCR accessors we provide access to GIC CPU interface state >> to userland by wiring it up to the existing userland interface. >> [Marc: move and make VMCR accessors

Re: [PATCH v3 47/55] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access

On Fri, May 06, 2016 at 11:46:00AM +0100, Andre Przywara wrote: > Using the VMCR accessors we provide access to GIC CPU interface state > to userland by wiring it up to the existing userland interface. > [Marc: move and make VMCR accessors static, streamline MMIO handlers] does this mean Marc did

Re: [PATCH v3 46/55] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors

On Fri, May 06, 2016 at 11:45:59AM +0100, Andre Przywara wrote: > Since the GIC CPU interface is always virtualized by the hardware, > we don't have CPU interface state information readily available in our > emulation if userland wants to save or restore it. > Fortunately the GIC hypervisor

Re: [PATCH v3 45/55] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers

On Fri, May 06, 2016 at 11:45:58AM +0100, Andre Przywara wrote: > Userland may want to save and restore the state of the in-kernel VGIC, > so we provide the code which takes a userland request and translate > that into calls to our MMIO framework. > > Signed-off-by: Andre Przywara

Re: [PATCH v3 43/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers

On Fri, May 06, 2016 at 11:45:56AM +0100, Andre Przywara wrote: > From: Eric Auger > > This patch implements the switches for KVM_DEV_ARM_VGIC_GRP_DIST_REGS > and KVM_DEV_ARM_VGIC_GRP_CPU_REGS API which allows the userspace to > access VGIC registers. > > Signed-off-by:

Re: [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework

Hi, On 12/05/16 12:46, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:30AM +0100, Andre Przywara wrote: >> From: Marc Zyngier >> >> Implement the framework for syncing IRQs between our emulation and >> the list registers, which represent the guest's view of IRQs.

Re: [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers

On 12/05/16 15:00, Andre Przywara wrote: > Hi, > > On 12/05/16 13:37, Marc Zyngier wrote: >> On 12/05/16 13:21, Christoffer Dall wrote: >>> On Fri, May 06, 2016 at 11:45:49AM +0100, Andre Przywara wrote: Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR register can

Re: [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions

On Thu, May 12, 2016 at 02:25:23PM +0100, Andre Przywara wrote: > Hi, > > On 12/05/16 13:12, Christoffer Dall wrote: > > On Fri, May 06, 2016 at 11:45:26AM +0100, Andre Przywara wrote: > >> From: Christoffer Dall > >> > >> Add a new header file for the new and

Re: [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers

On Thu, May 12, 2016 at 01:37:57PM +0100, Marc Zyngier wrote: > On 12/05/16 13:21, Christoffer Dall wrote: > > On Fri, May 06, 2016 at 11:45:49AM +0100, Andre Przywara wrote: > >> Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR > >> register can handle, the new IROUTER register

Re: [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions

Hi, On 12/05/16 13:12, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:26AM +0100, Andre Przywara wrote: >> From: Christoffer Dall >> >> Add a new header file for the new and improved GIC implementation. >> The big change is that we now have a struct vgic_irq

[PATCH] fixup! vgic-new: make vgic_register_redist_iodevs more readable

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic-mmio-v3.c | 42 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c index 97995e2..1985d56

Re: [PATCH v3 37/55] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler

On Fri, May 06, 2016 at 11:45:50AM +0100, Andre Przywara wrote: > In contrast to GICv2 SGIs in a GICv3 implementation are not triggered > by a MMIO write, but with a system register write. KVM knows about > that register already, we just need to implement the handler and wire > it up to the core

Re: [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers

On 12/05/16 13:21, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:49AM +0100, Andre Przywara wrote: >> Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR >> register can handle, the new IROUTER register covers the whole range >> of possible target (V)CPUs by using the same

Re: [PATCH v3 35/55] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler

Hi, On 12/05/16 13:12, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:48AM +0100, Andre Przywara wrote: >> We implement the only one ID register that is required by the >> architecture, also this is the one that Linux actually checks. >> >> Signed-off-by: Andre Przywara

Re: [PATCH v3 33/55] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers

Hi, On 12/05/16 12:47, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:46AM +0100, Andre Przywara wrote: >> As in the GICv2 emulation we handle those three registers in one >> function. >> >> Signed-off-by: Andre Przywara >> --- >> Changelog RFC..v1: >> - kick

Re: [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions

On Thu, May 12, 2016 at 01:17:38PM +0100, Marc Zyngier wrote: > On 12/05/16 13:12, Christoffer Dall wrote: > > On Fri, May 06, 2016 at 11:45:26AM +0100, Andre Przywara wrote: > >> From: Christoffer Dall > >> > >> Add a new header file for the new and improved GIC

Re: [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers

On Fri, May 06, 2016 at 11:45:49AM +0100, Andre Przywara wrote: > Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR > register can handle, the new IROUTER register covers the whole range > of possible target (V)CPUs by using the same MPIDR that the cores > report themselves. > In

Re: [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions

On 12/05/16 13:12, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:26AM +0100, Andre Przywara wrote: >> From: Christoffer Dall >> >> Add a new header file for the new and improved GIC implementation. >> The big change is that we now have a struct vgic_irq per

Re: [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions

On Fri, May 06, 2016 at 11:45:26AM +0100, Andre Przywara wrote: > From: Christoffer Dall > > Add a new header file for the new and improved GIC implementation. > The big change is that we now have a struct vgic_irq per IRQ instead > of spreading all the information

Re: [PATCH v3 35/55] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler

On Fri, May 06, 2016 at 11:45:48AM +0100, Andre Przywara wrote: > We implement the only one ID register that is required by the > architecture, also this is the one that Linux actually checks. > > Signed-off-by: Andre Przywara > --- > Changelog v1 .. v2: > - adapt to new

Re: [PATCH v3 34/55] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler

On Fri, May 06, 2016 at 11:45:47AM +0100, Andre Przywara wrote: > The redistributor TYPER tells the OS about the associated MPIDR, > also the LAST bit is crucial to determine the number of redistributors. > > Signed-off-by: Andre Przywara > --- > Changelog v1 .. v2: > -

Re: [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework

On Fri, May 06, 2016 at 11:45:30AM +0100, Andre Przywara wrote: > From: Marc Zyngier > > Implement the framework for syncing IRQs between our emulation and > the list registers, which represent the guest's view of IRQs. > This is done in kvm_vgic_flush_hwstate and

Re: [PATCH v3 33/55] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers

On Fri, May 06, 2016 at 11:45:46AM +0100, Andre Przywara wrote: > As in the GICv2 emulation we handle those three registers in one > function. > > Signed-off-by: Andre Przywara > --- > Changelog RFC..v1: > - kick VCPUs if distributor gets enabled > > Changelog v1 .. v2:

Re: [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework

Hi, On 12/05/16 11:26, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:45AM +0100, Andre Przywara wrote: >> Create a new file called vgic-mmio-v3.c and describe the GICv3 >> distributor and redistributor registers there. >> This adds a special macro to deal with the split of SGI/PPI in

Re: [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework

On Fri, May 06, 2016 at 11:45:45AM +0100, Andre Przywara wrote: > Create a new file called vgic-mmio-v3.c and describe the GICv3 > distributor and redistributor registers there. > This adds a special macro to deal with the split of SGI/PPI in the > redistributor and SPIs in the distributor, which

Re: [PATCH v3 27/55] KVM: arm/arm64: vgic-new: Add PRIORITY registers handlers

On 12 May 2016 at 10:10, Marc Zyngier wrote: > This is wrong. We should only write the number of bits of priority we > actually emulate. And given that we use a common framework for v2 and > v3, this should probably be 5 bits (32 priorities should be enough for > everybody).

Re: [PATCH v3 27/55] KVM: arm/arm64: vgic-new: Add PRIORITY registers handlers

On 06/05/16 11:45, Andre Przywara wrote: > The priority register handlers are shared between the v2 and v3 > emulation, so their implementation goes into vgic-mmio.c, to be > easily referenced from the v3 emulation as well later. > There is a corner case when we change the priority of a pending >

Re: [PATCH v3 31/55] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers

On Fri, May 06, 2016 at 11:45:44AM +0100, Andre Przywara wrote: > As this register is v2 specific, its implementation lives entirely > in vgic-mmio-v2.c. > This register allows setting the source mask of an IPI. > > Signed-off-by: Andre Przywara > --- > Changelog RFC..v1:

Re: [PATCH v3 29/55] KVM: arm/arm64: vgic-new: Add TARGET registers handlers

On Thu, May 12, 2016 at 10:35:49AM +0200, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:42AM +0100, Andre Przywara wrote: > > The target register handlers are v2 emulation specific, so their > > implementation lives entirely in vgic-mmio-v2.c. > > We copy the old VGIC behaviour of

Re: [PATCH v3 30/55] KVM: arm/arm64: vgic-new: Add SGIR register handler

On Fri, May 06, 2016 at 11:45:43AM +0100, Andre Przywara wrote: > Triggering an IPI via this register is v2 specific, so the > implementation lives entirely in vgic-mmio-v2.c. > > Signed-off-by: Andre Przywara > --- > Changelog RFC..v1: > - silently return on illegal

Re: [PATCH v3 29/55] KVM: arm/arm64: vgic-new: Add TARGET registers handlers

On 12/05/16 09:35, Christoffer Dall wrote: > On Fri, May 06, 2016 at 11:45:42AM +0100, Andre Przywara wrote: >> The target register handlers are v2 emulation specific, so their >> implementation lives entirely in vgic-mmio-v2.c. >> We copy the old VGIC behaviour of assigning an IRQ to the first

Re: [PATCH v3 29/55] KVM: arm/arm64: vgic-new: Add TARGET registers handlers

On Fri, May 06, 2016 at 11:45:42AM +0100, Andre Przywara wrote: > The target register handlers are v2 emulation specific, so their > implementation lives entirely in vgic-mmio-v2.c. > We copy the old VGIC behaviour of assigning an IRQ to the first VCPU > set in the target mask instead of making it

Re: [PATCH v3 28/55] KVM: arm/arm64: vgic-new: Add CONFIG registers handlers

On Fri, May 06, 2016 at 11:45:41AM +0100, Andre Przywara wrote: > The config register handlers are shared between the v2 and v3 > emulation, so their implementation goes into vgic-mmio.c, to be > easily referenced from the v3 emulation as well later. > > Signed-off-by: Andre Przywara