From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-its.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrast
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts. For this ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
is defined.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 44 +
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
To test live migrati
On 24 August 2016 at 11:19, Suzuki K Poulose wrote:
> On 24/08/16 10:23, Shannon Zhao wrote:
>> Yes, this works for qemu with "-cpu host". But if it specifies the cpu
>> type with "-cpu cortex-a72". It will fail without this patch.
>
>
> Thats because you specify the expected target from the kerne
Will Deacon writes:
> Hi Punit,
>
> On Tue, Aug 16, 2016 at 11:45:11AM +0100, Punit Agrawal wrote:
>> The ARMv8 architecture allows trapping of TLB maintenane instructions
>> from EL0/EL1 to higher exception levels. On encountering a trappable TLB
>> instruction in a guest, an exception is taken
On 24/08/16 10:23, Shannon Zhao wrote:
On 2016/8/24 16:57, Suzuki K Poulose wrote:
On 24/08/16 08:21, Shannon Zhao wrote:
In order to allow KVM to run on Cortex-A72 physical cpus, enable KVM
support for Cortex-A72.
Do we really need this change ? Given that A72 is using the generic_v8
table
On 2016/8/24 16:57, Suzuki K Poulose wrote:
> On 24/08/16 08:21, Shannon Zhao wrote:
>> In order to allow KVM to run on Cortex-A72 physical cpus, enable KVM
>> support for Cortex-A72.
>
> Do we really need this change ? Given that A72 is using the generic_v8
> table,
> it will automatically be s
On Wed, 24 Aug 2016 15:21:37 +0800
Shannon Zhao wrote:
Hi Shannon,
> In order to allow KVM to run on Cortex-A72 physical cpus, enable KVM
> support for Cortex-A72.
>
> Signed-off-by: Shannon Zhao
Why do we need any of this?
Since bca556ac468a ("arm64/kvm: Add generic v8 KVM target"), we supp
On 24/08/16 08:21, Shannon Zhao wrote:
In order to allow KVM to run on Cortex-A72 physical cpus, enable KVM
support for Cortex-A72.
Do we really need this change ? Given that A72 is using the generic_v8 table,
it will automatically be supported via the GENERIC_V8 target. That was added
just for
In order to allow KVM to run on Cortex-A72 physical cpus, enable KVM
support for Cortex-A72.
Signed-off-by: Shannon Zhao
---
arch/arm64/include/asm/cputype.h | 1 +
arch/arm64/include/uapi/asm/kvm.h| 3 ++-
arch/arm64/kvm/guest.c | 2 ++
arch/arm64/kvm/sys_regs_generic_v8.c
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