On Mon, Sep 05, 2016 at 05:31:35PM +0100, Punit Agrawal wrote:
> From: Mark Rutland
>
> Now that we have a __tlbi() helper, make use of this in the arm64 KVM hyp
> code to get rid of asm() boilerplate. At the same time, we simplify
> __tlb_flush_vm_context by using __flush_icache_all(), as this h
On Mon, Sep 05, 2016 at 05:31:34PM +0100, Punit Agrawal wrote:
> From: Mark Rutland
>
> As with dsb() and isb(), add a __tlbi() helper so that we can avoid
> distracting asm boilerplate every time we want a TLBI. As some TLBI
> operations take an argument while others do not, some pre-processor i
On Mon, Sep 05, 2016 at 05:31:33PM +0100, Punit Agrawal wrote:
> Register a notifier to track state changes of perf trace events.
>
> The notifier will enable taking appropriate action for trace events
> targeting VM.
>
> Signed-off-by: Punit Agrawal
> Cc: Christoffer Dall
> Cc: Marc Zyngier
On Mon, Sep 05, 2016 at 05:31:32PM +0100, Punit Agrawal wrote:
> Userspace tools such as perf can be used to profile individual
> processes.
>
> Track the PID of the virtual machine process to match profiling requests
> targeted at it. This can be used to take appropriate action to enable
> the re
Add a mechanism to notify listeners about perf trace event state
changes. This enables listeners to take actions requiring the event
context (e.g., attached process).
The notification mechanism can be used to reduce trace point based
profiling overhead by enabling/disabling hardware traps for spec
From: Mark Rutland
Now that we have a __tlbi() helper, make use of this in the arm64 KVM hyp
code to get rid of asm() boilerplate. At the same time, we simplify
__tlb_flush_vm_context by using __flush_icache_all(), as this has the
appropriate instruction cache maintenance and barrier.
Signed-off
Register a notifier to track state changes of perf trace events.
The notifier will enable taking appropriate action for trace events
targeting VM.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
---
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kvm/arm.c
From: Mark Rutland
As with dsb() and isb(), add a __tlbi() helper so that we can avoid
distracting asm boilerplate every time we want a TLBI. As some TLBI
operations take an argument while others do not, some pre-processor is
used to handle these two cases with different assembly blocks.
The exi
The TTLB bit of Hypervisor Control Register (HCR_EL2) controls the
trapping of guest TLB maintenance instructions. Taking the trap requires
a switch to the hypervisor and is an expensive operation.
Enable selective trapping of guest TLB instructions when the associated
perf trace event is enabled
The ARMv8 architecture allows trapping of TLB maintenane instructions
from EL0/EL1 to higher exception levels. On encountering a trappable TLB
instruction in a guest, an exception is taken to EL2.
Add functionality to handle emulating the TLB instructions.
Signed-off-by: Punit Agrawal
Cc: Christ
Userspace tools such as perf can be used to profile individual
processes.
Track the PID of the virtual machine process to match profiling requests
targeted at it. This can be used to take appropriate action to enable
the requested profiling operations for the VMs of interest.
Signed-off-by: Punit
Hi,
Although there are no PMU events to monitor TLB operations, ARMv8
supports trapping guest TLB maintenance operations to the
hypervisor. This trapping mechanism can be used to monitor the use of
guest TLB instructions.
As taking a trap for every TLB operation can have significant
overhead, tra
On Tue, Aug 16, 2016 at 11:46:58AM +0100, Vladimir Murzin wrote:
> It is time to get access to common version of vgic-v3.
common version?
>
> We basically would need to tell build system how to pick it up and
> undo KVM_ARM_VGIC_V3 guarding introduced in 4f64cb6 ("arm/arm64: KVM:
> Only allow 64
On Tue, Aug 16, 2016 at 11:46:52AM +0100, Vladimir Murzin wrote:
> Since we are going to share vgic-v3 save/restore code with ARM
> keep arch specific accessors separately.
>
> Signed-off-by: Vladimir Murzin
Acked-by: Christoffer Dall
___
kvmarm maili
On Tue, Aug 16, 2016 at 11:46:57AM +0100, Vladimir Murzin wrote:
> We need to take care we have everything vgic-v3 expects from us before
> a quantum leap:
> - provide required macros via uapi.h
> - handle access to GICv3 cpu interface from the guest
> - provide mapping between arm64 version of GIC
The title of this patch is quite generic, especially the 'update'.
Perhaps say:
"ARM: Change MPIDR_AFFINITY_LEVEL to ignore Aff3"
On Tue, Aug 16, 2016 at 11:46:55AM +0100, Vladimir Murzin wrote:
> vgic-v3 driver queries CPU affinity level up to Aff3, which is valid for
> arm64.
> However, for a
On Tue, Aug 16, 2016 at 11:46:56AM +0100, Vladimir Murzin wrote:
> Macro __ACCESS_CP15{_64} is defined in two headers (arch_gicv3.h and
> kvm_hyp.h) which are going to be requested by vgic-v3 altogether.
> GCC would not like it because it'd see that macro is redefined and (hey!)
> they are differen
Hi Vladimir,
I think commit title is too vague, can you be more specific?
On Tue, Aug 16, 2016 at 11:46:54AM +0100, Vladimir Murzin wrote:
> We have couple of 64-bit register defined in GICv3 architecture, so
'a couple', 'registers' (plural)
> "unsigned long" kind of accessors wouldn't work fo
On Tue, Aug 16, 2016 at 11:46:51AM +0100, Vladimir Murzin wrote:
> Hi,
>
> This is an attempt to make use vgic-v3 under arch/arm since save-restore
> functionality got re-written in C and can be shared between arm/arm64
> like it has already been done for vgic-v2 and timer.
>
> With this patches
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