On Tue, Sep 06, 2016 at 07:42:19PM +0530, Vijay Kilari wrote:
> On Tue, Aug 30, 2016 at 7:30 PM, Christoffer Dall
> wrote:
> >
> > On Wed, Aug 24, 2016 at 04:50:09PM +0530, vijay.kil...@gmail.com wrote:
> > > From: Vijaya Kumar K
> > > }
> > > diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> > >
On Tue, Sep 06, 2016 at 07:43:23PM +0530, Vijay Kilari wrote:
> Resending in plain text mode
>
> On Tue, Sep 6, 2016 at 7:18 PM, Vijay Kilari wrote:
> >
> >
> > On Tue, Aug 30, 2016 at 7:15 PM, Christoffer Dall
> > wrote:
> >>
> >> On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com
On Mon, Sep 05, 2016 at 05:31:34PM +0100, Punit Agrawal wrote:
> From: Mark Rutland
>
> As with dsb() and isb(), add a __tlbi() helper so that we can avoid
> distracting asm boilerplate every time we want a TLBI. As some TLBI
> operations take an argument while others do not, some pre-processor i
On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> VGICv3 CPU interface registers are accessed using
> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> as 64-bit. The cpu MPIDR value is passed along with register id.
> is used to i
On Tue, Sep 06, 2016 at 07:44:15PM +0530, Vijay Kilari wrote:
> Resending in plain text mode
>
> On Tue, Sep 6, 2016 at 7:17 PM, Vijay Kilari wrote:
> >
> >
> > On Tue, Aug 30, 2016 at 6:01 PM, Christoffer Dall
> > wrote:
> >>
> >> On Wed, Aug 24, 2016 at 04:50:06PM +0530, vijay.kil...@gmail.com
Christoffer Dall writes:
> On Tue, Sep 06, 2016 at 04:22:17PM +0100, Punit Agrawal wrote:
>> Christoffer Dall writes:
>>
>> > On Tue, Sep 06, 2016 at 12:07:59PM +0100, Punit Agrawal wrote:
>> >> Christoffer Dall writes:
>> >>
>> >> > On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wro
On Tue, Sep 6, 2016 at 6:44 PM, Robin Murphy wrote:
> Hi Christoffer,
>
> On 06/09/16 17:41, Christoffer Dall wrote:
>> On Wed, Aug 17, 2016 at 01:32:49PM +0200, Christoffer Dall wrote:
>>> Hi Russell,
>>>
>>> On Tue, Aug 16, 2016 at 06:49:18PM +0100, Robin Murphy wrote:
Since the non-secure
On Tue, Sep 06, 2016 at 04:44:11PM +0100, Punit Agrawal wrote:
> Christoffer Dall writes:
>
> > On Mon, Sep 05, 2016 at 05:31:36PM +0100, Punit Agrawal wrote:
> >> The ARMv8 architecture allows trapping of TLB maintenane instructions
> >> from EL0/EL1 to higher exception levels. On encountering a
On Tue, Sep 06, 2016 at 04:22:17PM +0100, Punit Agrawal wrote:
> Christoffer Dall writes:
>
> > On Tue, Sep 06, 2016 at 12:07:59PM +0100, Punit Agrawal wrote:
> >> Christoffer Dall writes:
> >>
> >> > On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wrote:
> >> >> Hi Christoffer,
> >> >>
On Tue, Sep 06, 2016 at 02:23:16PM +0100, Vladimir Murzin wrote:
>
> Sorry, missed this one
>
> On 05/09/16 12:29, Christoffer Dall wrote:
> >>
> >> > +static bool __hyp_text __has_useable_gicv3_cpuif(void)
> >> > +{
> >> > +if (IS_ENABLED(CONFIG_ARM_GIC_V3) && (read_sysreg(ID_PFR1) >>
Hi Christoffer,
On 06/09/16 17:41, Christoffer Dall wrote:
> On Wed, Aug 17, 2016 at 01:32:49PM +0200, Christoffer Dall wrote:
>> Hi Russell,
>>
>> On Tue, Aug 16, 2016 at 06:49:18PM +0100, Robin Murphy wrote:
>>> Since the non-secure copies of banked registers lack architecturally
>>> defined res
On Tue, Sep 06, 2016 at 02:18:10PM +0100, Vladimir Murzin wrote:
> On 05/09/16 12:29, Christoffer Dall wrote:
> > On Tue, Aug 16, 2016 at 11:46:58AM +0100, Vladimir Murzin wrote:
> >> It is time to get access to common version of vgic-v3.
> >
> > common version?
> >
>
> Since patch#2 it not priv
On Tue, Sep 06, 2016 at 02:12:39PM +0100, Vladimir Murzin wrote:
> On 05/09/16 12:29, Christoffer Dall wrote:
> > On Tue, Aug 16, 2016 at 11:46:57AM +0100, Vladimir Murzin wrote:
> >> We need to take care we have everything vgic-v3 expects from us before
> >> a quantum leap:
> >> - provide required
On Wed, Aug 17, 2016 at 01:32:49PM +0200, Christoffer Dall wrote:
> Hi Russell,
>
> On Tue, Aug 16, 2016 at 06:49:18PM +0100, Robin Murphy wrote:
> > Since the non-secure copies of banked registers lack architecturally
> > defined reset values, there is no actual guarantee when entering in Hyp
> >
On Tue, Sep 06, 2016 at 02:05:30PM +0100, Vladimir Murzin wrote:
> On 05/09/16 12:29, Christoffer Dall wrote:
> > On Tue, Aug 16, 2016 at 11:46:56AM +0100, Vladimir Murzin wrote:
> >> Macro __ACCESS_CP15{_64} is defined in two headers (arch_gicv3.h and
> >> kvm_hyp.h) which are going to be requeste
On Tue, Sep 06, 2016 at 02:54:01PM +0100, Vladimir Murzin wrote:
> On 06/09/16 14:22, Christoffer Dall wrote:
> > On Tue, Sep 06, 2016 at 01:41:37PM +0100, Vladimir Murzin wrote:
> >> Hi Christoffer,
> >>
> >> On 05/09/16 12:29, Christoffer Dall wrote:
> >>> Hi Vladimir,
> >>>
> >>> I think commit
Christoffer Dall writes:
> On Mon, Sep 05, 2016 at 05:31:33PM +0100, Punit Agrawal wrote:
>> Register a notifier to track state changes of perf trace events.
>>
>> The notifier will enable taking appropriate action for trace events
>> targeting VM.
>>
>> Signed-off-by: Punit Agrawal
>> Cc: Chr
Christoffer Dall writes:
> On Mon, Sep 05, 2016 at 05:31:36PM +0100, Punit Agrawal wrote:
>> The ARMv8 architecture allows trapping of TLB maintenane instructions
>> from EL0/EL1 to higher exception levels. On encountering a trappable TLB
>> instruction in a guest, an exception is taken to EL2.
>
Christoffer Dall writes:
> On Tue, Sep 06, 2016 at 12:07:59PM +0100, Punit Agrawal wrote:
>> Christoffer Dall writes:
>>
>> > On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wrote:
>> >> Hi Christoffer,
>> >>
>> >> Christoffer Dall writes:
>> >>
>> >> > On Mon, Sep 05, 2016 at 05:31:
Resending in plain text mode
On Tue, Sep 6, 2016 at 7:17 PM, Vijay Kilari wrote:
>
>
> On Tue, Aug 30, 2016 at 6:01 PM, Christoffer Dall
> wrote:
>>
>> On Wed, Aug 24, 2016 at 04:50:06PM +0530, vijay.kil...@gmail.com wrote:
>> > From: Vijaya Kumar K
>> >
>> > VGICv3 Distributor and Redistributo
Resending in plain text mode
On Tue, Sep 6, 2016 at 7:18 PM, Vijay Kilari wrote:
>
>
> On Tue, Aug 30, 2016 at 7:15 PM, Christoffer Dall
> wrote:
>>
>> On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com wrote:
>> > From: Vijaya Kumar K
>
>
>>
>> > diff --git a/virt/kvm/arm/vgic/vg
On Tue, Aug 30, 2016 at 7:30 PM, Christoffer Dall
wrote:
>
> On Wed, Aug 24, 2016 at 04:50:09PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
> > }
> > diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c
> > b/virt/kvm/arm/vgic/vgic-mmio-v3.c
> > index 61abea0..fde1472 100644
> > ---
On 06/09/16 14:22, Christoffer Dall wrote:
> On Tue, Sep 06, 2016 at 01:41:37PM +0100, Vladimir Murzin wrote:
>> Hi Christoffer,
>>
>> On 05/09/16 12:29, Christoffer Dall wrote:
>>> Hi Vladimir,
>>>
>>> I think commit title is too vague, can you be more specific?
>>>
>>
>> KVM: arm: vgic-new: make
On Tue, Aug 30, 2016 at 7:15 PM, Christoffer Dall <
christoffer.d...@linaro.org> wrote:
> On Wed, Aug 24, 2016 at 04:50:08PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
>
> > diff --git a/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> b/virt/kvm/arm/vgic/vgic-sys-reg-v3.c
> > new file
On Tue, Aug 30, 2016 at 6:01 PM, Christoffer Dall <
christoffer.d...@linaro.org> wrote:
> On Wed, Aug 24, 2016 at 04:50:06PM +0530, vijay.kil...@gmail.com wrote:
> > From: Vijaya Kumar K
> >
> > VGICv3 Distributor and Redistributor registers are accessed using
> > KVM_DEV_ARM_VGIC_GRP_DIST_REGS a
Sorry, missed this one
On 05/09/16 12:29, Christoffer Dall wrote:
>>
>> > +static bool __hyp_text __has_useable_gicv3_cpuif(void)
>> > +{
>> > + if (IS_ENABLED(CONFIG_ARM_GIC_V3) && (read_sysreg(ID_PFR1) >> 28))
> Do we have a define for bit 28 we could use?
I'll check it.
>
> Does this act
On Tue, Sep 06, 2016 at 01:41:37PM +0100, Vladimir Murzin wrote:
> Hi Christoffer,
>
> On 05/09/16 12:29, Christoffer Dall wrote:
> > Hi Vladimir,
> >
> > I think commit title is too vague, can you be more specific?
> >
>
> KVM: arm: vgic-new: make extract_bytes to always work on 64-bit data
>
On 05/09/16 12:29, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:58AM +0100, Vladimir Murzin wrote:
>> It is time to get access to common version of vgic-v3.
>
> common version?
>
Since patch#2 it not private to arm64 or I should rephrase this?
>>
>> We basically would need to tell bu
On 05/09/16 12:29, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:57AM +0100, Vladimir Murzin wrote:
>> We need to take care we have everything vgic-v3 expects from us before
>> a quantum leap:
>> - provide required macros via uapi.h
>> - handle access to GICv3 cpu interface from the guest
On 05/09/16 12:29, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:58AM +0100, Vladimir Murzin wrote:
>> It is time to get access to common version of vgic-v3.
>
> common version?
>
>>
>> We basically would need to tell build system how to pick it up and
>> undo KVM_ARM_VGIC_V3 guarding i
On 05/09/16 12:29, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:56AM +0100, Vladimir Murzin wrote:
>> Macro __ACCESS_CP15{_64} is defined in two headers (arch_gicv3.h and
>> kvm_hyp.h) which are going to be requested by vgic-v3 altogether.
>> GCC would not like it because it'd see that m
As we know handle external aborts pretty early, we can get rid of
its handling in the MMIO code (which was a bit odd to begin with...).
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/mmio.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 10f
An asynchronous abort can also be triggered whilst running at EL2.
But instead of making that a new error code, we need to communicate
it to the rest of KVM together with the exit reason.
So let's hijack a single bit that allows the exception code to be
tagged with a "pending Abort" information.
S
Now that we're able to context switch the HCR.VA bit, let's
introduce a helper that injects an Abort into a vcpu.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_emulate.h | 1 +
arch/arm/kvm/emulate.c | 12
2 files changed, 13 insertions(+)
diff --git a/arch/
Just like for arm64, we can handle asynchronous aborts being
delivered at HYP while being caused by the guest. We use
the exact same method to catch such an abort, and soldier on.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/hyp/entry.S | 31 +++
arch/arm/kvm/hyp/
If we spot a data abort bearing the ESR_EL2.EA bit set, we know that
this is an external abort, and that should be punished by a the injection
of an abort.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/mmu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kv
As we now have some basic handling to EL1-triggered aborts, we can
actually report them to KVM.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/hyp-entry.S | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-e
Both data and prefetch aborts occuring in HYP lead to a well
deserved panic. Let's get rid of these silly handlers.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/handle_exit.c | 27 ---
1 file changed, 27 deletions(-)
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm
If, when proxying a GICV access at EL2, we detect that the guest is
doing something silly, report an EL1 SError instead ofgnoring the
access.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_hyp.h | 2 +-
arch/arm64/kvm/hyp/switch.c | 18 +++---
virt/kvm/arm/hyp/vgic-
The HCR.VA bit is used to signal an Abort to a guest, and has
the peculiar feature of getting cleared when the guest has taken
the abort (this is the only bit that behaves as such in this register).
This means that if we signal such an abort, we must leave it in
the guest context until it disappea
If we have caught an SError whilst exiting, we've tagged the
exit code with the pending information. In that case, let's
re-inject the error into the guest, after having adjusted
the PC if required.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/handle_exit.c | 20
1 file ch
If we have caught an Abort whilst exiting, we've tagged the
exit code with the pending information. In that case, let's
re-inject the error into the guest, after having adjusted
the PC if required.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/handle_exit.c | 19 +++
1 file change
If we've exited the guest because it has triggered an asynchronous
abort, a possible course of action is to let it know it screwed up
by giving it a Virtual Abort to chew on.
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/handle_exit.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/ar
If EL1 generates an asynchronous abort and then traps into EL2
before the abort has been delivered, we may end-up with the
abort firing at the worse possible place: on the host.
In order to avoid this, it is necessary to take the abort at EL2,
by clearing the PSTATE.A bit. In order to survive this
Similarily to EL1, an asynchronous abort can be triggered whilst
running at EL2. But instead of making that a new error code,
we need to communicate it to the rest of KVM together with
the exit reason. So let's hijack a single bit that allows the
exception code to be tagged with a "pending SError"
So far, we don't have a code to indicate that we've taken an
asynchronous abort from EL1. Let's add one.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include
Now that we're able to context switch the HCR_EL2.VA bit, let's
introduce a helper that injects an Abort into a vcpu.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 1 +
arch/arm64/kvm/inject_fault.c| 12
2 files changed, 13 insertions(+)
diff --git
If we've exited the guest because it has triggered an asynchronous
abort from EL1, a possible course of action is to let it know it
screwed up by giving it a Virtual Abort to chew on.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/handle_exit.c | 3 +++
1 file changed, 3 insertions(+)
diff --gi
The HCR_EL2.VSE bit is used to signal an SError to a guest, and has
the peculiar feature of getting cleared when the guest has taken
the abort (this is the only bit that behaves as such in this register).
This means that if we signal such an abort, we must leave it
in the guest context until it di
A little known "feature" of giving guest access to real memory mapped
HW is that it could trigger asynchronous aborts (SError on ARMv8) if
the guest accesses it in a non-conventional way (and depending on how
HW and firmware have been integrated). So far, KVM lacks any support
to handle this gracef
HCR_VA is a leftover from ARMv7, On ARMv8, this is HCR_VSE
(which stands for Virtual System Error), and has better
defined semantics.
Let's rename the constant.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_arm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 05/09/16 12:29, Christoffer Dall wrote:
> The title of this patch is quite generic, especially the 'update'.
> Perhaps say:
>
> "ARM: Change MPIDR_AFFINITY_LEVEL to ignore Aff3"
>
Fixed.
> On Tue, Aug 16, 2016 at 11:46:55AM +0100, Vladimir Murzin wrote:
>> vgic-v3 driver queries CPU affinit
Hi Christoffer,
On 05/09/16 12:29, Christoffer Dall wrote:
> Hi Vladimir,
>
> I think commit title is too vague, can you be more specific?
>
KVM: arm: vgic-new: make extract_bytes to always work on 64-bit data
is it better?
> On Tue, Aug 16, 2016 at 11:46:54AM +0100, Vladimir Murzin wrote:
>>
On 05/09/16 12:28, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:51AM +0100, Vladimir Murzin wrote:
>> Hi,
>>
>> This is an attempt to make use vgic-v3 under arch/arm since save-restore
>> functionality got re-written in C and can be shared between arm/arm64
>> like it has already been do
On 05/09/16 12:28, Christoffer Dall wrote:
> On Tue, Aug 16, 2016 at 11:46:52AM +0100, Vladimir Murzin wrote:
>> Since we are going to share vgic-v3 save/restore code with ARM
>> keep arch specific accessors separately.
>>
>> Signed-off-by: Vladimir Murzin
>
> Acked-by: Christoffer Dall
>
>
T
Christoffer Dall writes:
> On Mon, Sep 05, 2016 at 05:31:37PM +0100, Punit Agrawal wrote:
>> The TTLB bit of Hypervisor Control Register (HCR_EL2) controls the
>> trapping of guest TLB maintenance instructions. Taking the trap requires
>> a switch to the hypervisor and is an expensive operation.
On Tue, Sep 06, 2016 at 12:07:59PM +0100, Punit Agrawal wrote:
> Christoffer Dall writes:
>
> > On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wrote:
> >> Hi Christoffer,
> >>
> >> Christoffer Dall writes:
> >>
> >> > On Mon, Sep 05, 2016 at 05:31:32PM +0100, Punit Agrawal wrote:
> >>
On Tue, Sep 06, 2016 at 09:28:40AM +0100, Marc Zyngier wrote:
> In a number of cases, KVM cannot give access direct access to the
> GICv2 GICV region, either because GICV is not page aligned, or its
> size is not a multiple of the page size. This is especially visible
> with 16kB/64kB pages and the
Christoffer Dall writes:
> On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wrote:
>> Hi Christoffer,
>>
>> Christoffer Dall writes:
>>
>> > On Mon, Sep 05, 2016 at 05:31:32PM +0100, Punit Agrawal wrote:
>> >> Userspace tools such as perf can be used to profile individual
>> >> processe
On Tue, Sep 06, 2016 at 09:28:44AM +0100, Marc Zyngier wrote:
> As we plan to do some emulation at HYP, let's make kvm_skip_instr32
> as part of the hyp_text section. This doesn't preclude the kernel
> from using it.
>
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
___
On Tue, Sep 06, 2016 at 09:28:45AM +0100, Marc Zyngier wrote:
> In order to efficiently perform the GICV access on behalf of the
> guest, we need to be able to avoid going back all the way to
> the host kernel.
>
> For this, we introduce a new hook in the world switch code,
> conveniently placed j
On Tue, Sep 06, 2016 at 09:28:43AM +0100, Marc Zyngier wrote:
> Add the bit of glue and const-ification that is required to use
> the code inherited from the arm64 port, and move over to it.
>
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
_
On Tue, Sep 06, 2016 at 09:28:41AM +0100, Marc Zyngier wrote:
> In order to make emulate.c more generic, move the arch-specific
> manupulation bits out of emulate.c.
>
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
___
kvmarm mailing list
kv
On Tue, Sep 06, 2016 at 09:28:42AM +0100, Marc Zyngier wrote:
> It would make some sense to share the conditional execution code
> between 32 and 64bit. In order to achieve this, let's move that
> code to virt/kvm/arm/aarch32.c. While we're at it, drop a
> superfluous BUG_ON() that wasn't that usef
On Tue, Sep 06, 2016 at 11:05:17AM +0100, Punit Agrawal wrote:
> Christoffer Dall writes:
>
> > On Mon, Sep 05, 2016 at 05:31:34PM +0100, Punit Agrawal wrote:
> >> From: Mark Rutland
> >>
> >> As with dsb() and isb(), add a __tlbi() helper so that we can avoid
> >> distracting asm boilerplate e
On Tue, Sep 06, 2016 at 10:51:27AM +0100, Punit Agrawal wrote:
> Hi Christoffer,
>
> Christoffer Dall writes:
>
> > On Mon, Sep 05, 2016 at 05:31:32PM +0100, Punit Agrawal wrote:
> >> Userspace tools such as perf can be used to profile individual
> >> processes.
> >>
> >> Track the PID of the v
On Mon, Sep 05, 2016 at 05:31:37PM +0100, Punit Agrawal wrote:
> The TTLB bit of Hypervisor Control Register (HCR_EL2) controls the
> trapping of guest TLB maintenance instructions. Taking the trap requires
> a switch to the hypervisor and is an expensive operation.
>
> Enable selective trapping o
On Mon, Sep 05, 2016 at 05:31:36PM +0100, Punit Agrawal wrote:
> The ARMv8 architecture allows trapping of TLB maintenane instructions
> from EL0/EL1 to higher exception levels. On encountering a trappable TLB
> instruction in a guest, an exception is taken to EL2.
>
> Add functionality to handle
Christoffer Dall writes:
> On Mon, Sep 05, 2016 at 05:31:34PM +0100, Punit Agrawal wrote:
>> From: Mark Rutland
>>
>> As with dsb() and isb(), add a __tlbi() helper so that we can avoid
>> distracting asm boilerplate every time we want a TLBI. As some TLBI
>> operations take an argument while o
Hi Christoffer,
Christoffer Dall writes:
> On Mon, Sep 05, 2016 at 05:31:32PM +0100, Punit Agrawal wrote:
>> Userspace tools such as perf can be used to profile individual
>> processes.
>>
>> Track the PID of the virtual machine process to match profiling requests
>> targeted at it. This can be
On 06/09/16 08:51, Itaru Kitayama wrote:
Hi,
Observed with kvm-arm-for-v4.8-rc3 when enabling memory debugging options on
top of defconfig. defconfig'ed kernel does not have
such issue though.
Below is the console log:
[ 757.644120] Unable to handle kernel paging request at virtual address
So far, we've been disabling KVM on systems where the GICV region couldn't
be safely given to a guest. Now that we're able to handle this access
safely by emulating it in HYP, we can enable this feature when we detect
an unsafe configuration.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyng
Now that we have the necessary infrastructure to handle MMIO accesses
in HYP, perform the GICV access on behalf of the guest. This requires
checking that the access is strictly 32bit, properly aligned, and
falls within the expected range.
When all condition are satisfied, we perform the access and
As we plan to do some emulation at HYP, let's make kvm_skip_instr32
as part of the hyp_text section. This doesn't preclude the kernel
from using it.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/aarch32.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/aarch3
It would make some sense to share the conditional execution code
between 32 and 64bit. In order to achieve this, let's move that
code to virt/kvm/arm/aarch32.c. While we're at it, drop a
superfluous BUG_ON() that wasn't that useful.
Following patches will migrate the 32bit port to that code base.
In order to efficiently perform the GICV access on behalf of the
guest, we need to be able to avoid going back all the way to
the host kernel.
For this, we introduce a new hook in the world switch code,
conveniently placed just after populating the fault info.
At that point, we only have saved/res
In a number of cases, KVM cannot give access direct access to the
GICv2 GICV region, either because GICV is not page aligned, or its
size is not a multiple of the page size. This is especially visible
with 16kB/64kB pages and the original GIC-400 layout where each region
is only 4k aligned.
Instea
Add the bit of glue and const-ification that is required to use
the code inherited from the arm64 port, and move over to it.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_emulate.h | 34 ++---
arch/arm/kvm/Makefile | 1 +
arch/arm/kvm/emulate.c | 97 -
In order to make emulate.c more generic, move the arch-specific
manupulation bits out of emulate.c.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 10 ++
arch/arm64/kvm/emulate.c | 11 ---
2 files changed, 10 insertions(+), 11 deletions(-)
dif
Hi,
Observed with kvm-arm-for-v4.8-rc3 when enabling memory debugging
options on top of defconfig. defconfig'ed kernel does not have
such issue though.
Below is the console log:
[ 757.644120] Unable to handle kernel paging request at virtual address
800661e0
[ 757.652046] pgd = ff
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