On Tue, Sep 13, 2016 at 11:16:06AM +0100, Punit Agrawal wrote:
> From: Mark Rutland
>
> As with dsb() and isb(), add a __tlbi() helper so that we can avoid
> distracting asm boilerplate every time we want a TLBI. As some TLBI
> operations take an argument while others do not, some pre-processor i
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 insertions(+), 2 deletions
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/vgic/vgic-kvm-device.c | 50
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
is used to identify the cpu for registers access.
The version of VGIC v3 specification is defin
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register o
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/445611.html
The patch 3 & 4 are
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
On 23/09/2016 14:40, Christoffer Dall wrote:
> On Fri, Sep 23, 2016 at 02:11:41PM +0200, Paolo Bonzini wrote:
>>
>>
>> On 23/09/2016 13:07, Alexander Graf wrote:
>>> + timer_ret = kvm_timer_sync_hwstate(vcpu);
>>>
>>> kvm_vgic_sync_hwstate(vcpu);
>>>
>>> pree
On 23/09/2016 14:36, Alexander Graf wrote:
>>>
>>> +if ((ret == 1) && timer_ret) {
>>> +/*
>>> + * We have to exit straight away to ensure that we only
>>> + * ever notify user space once about a level change
>>> + */
>>
>> Is this really a
On Fri, Sep 23, 2016 at 02:11:41PM +0200, Paolo Bonzini wrote:
>
>
> On 23/09/2016 13:07, Alexander Graf wrote:
> > + timer_ret = kvm_timer_sync_hwstate(vcpu);
> >
> > kvm_vgic_sync_hwstate(vcpu);
> >
> > preempt_enable();
> >
> > ret = handle_e
> Am 23.09.2016 um 14:11 schrieb Paolo Bonzini :
>
>
>
>> On 23/09/2016 13:07, Alexander Graf wrote:
>> +timer_ret = kvm_timer_sync_hwstate(vcpu);
>>
>>kvm_vgic_sync_hwstate(vcpu);
>>
>>preempt_enable();
>>
>>ret = handle_exit(vcpu, run, ret);
>> +
>> +
On 23/09/2016 13:07, Alexander Graf wrote:
> + timer_ret = kvm_timer_sync_hwstate(vcpu);
>
> kvm_vgic_sync_hwstate(vcpu);
>
> preempt_enable();
>
> ret = handle_exit(vcpu, run, ret);
> +
> + if ((ret == 1) && timer_ret) {
> +
On Fri, Sep 23, 2016 at 10:50:38AM +0100, Marc Zyngier wrote:
> On 22/09/16 15:01, Vijay Kilari wrote:
> > On Thu, Sep 22, 2016 at 5:38 PM, Marc Zyngier wrote:
> >> On 20/09/16 07:12, vijay.kil...@gmail.com wrote:
> >>> From: Vijaya Kumar K
> >>> +static int vgic_uaccess_read(struct kvm_vcpu *vcp
We have 2 modes for dealing with interrupts in the ARM world. We can either
handle them all using hardware acceleration through the vgic or we can emulate
a gic in user space and only drive CPU IRQ pins from there.
Unfortunately, when driving IRQs from user space, we never tell user space
about ti
On 22/09/16 15:01, Vijay Kilari wrote:
> On Thu, Sep 22, 2016 at 5:38 PM, Marc Zyngier wrote:
>> On 20/09/16 07:12, vijay.kil...@gmail.com wrote:
>>> From: Vijaya Kumar K
>>> +static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device
>>> *dev,
>>> + gpa_t
On 23/09/16 10:25, Christoffer Dall wrote:
> On Fri, Sep 23, 2016 at 03:13:25PM +0800, Alison Wang wrote:
>> The ARMv8 architecture supports two execution state, AArch64 and
>> AArch32. To support KVM in AArch32 execution state for ARMv8, Cortex-A53
>> and Cortex-A72 need to be added for target-spe
The ARMv8 architecture supports two execution state, AArch64 and
AArch32. To support KVM in AArch32 execution state for ARMv8, Cortex-A53
and Cortex-A72 need to be added for target-specific checks.
Signed-off-by: Alison Wang
---
arch/arm/include/asm/cputype.h | 2 ++
arch/arm/kvm/guest.c
On Fri, Sep 23, 2016 at 03:13:25PM +0800, Alison Wang wrote:
> The ARMv8 architecture supports two execution state, AArch64 and
> AArch32. To support KVM in AArch32 execution state for ARMv8, Cortex-A53
> and Cortex-A72 need to be added for target-specific checks.
>
> Signed-off-by: Alison Wang
>
On Fri, Sep 23, 2016 at 11:10:46AM +0200, Alexander Graf wrote:
>
>
> On 23.09.16 10:57, Paolo Bonzini wrote:
> >
> >
> > On 23/09/2016 09:14, Alexander Graf wrote:
> +/*
> + * Synchronize the timer IRQ state with the interrupt controller.
> + */
> static void kvm_timer_upd
On 23/09/2016 11:17, Alexander Graf wrote:
>> >
>> > On the other hand, what happens if you run new QEMU with old userspace?
>> > With user_timer_pending you'd get an infinite stream of vmexits the
>> > first time the timer fires, wouldn't you? Whereas if you keep it in the
>> > kernel, userspa
On 23.09.16 11:15, Paolo Bonzini wrote:
>
>
> On 23/09/2016 11:10, Alexander Graf wrote:
> Maybe I'm misunderstanding and user_timer_pending is just a cached
> verison of what you said last, but as I said above, I think you can just
> compare timer->irq.level with the last value the
On 23/09/2016 11:10, Alexander Graf wrote:
Maybe I'm misunderstanding and user_timer_pending is just a cached
verison of what you said last, but as I said above, I think you can just
compare timer->irq.level with the last value the kvm_run struct, and if
something changed, you
On 23.09.16 10:57, Paolo Bonzini wrote:
>
>
> On 23/09/2016 09:14, Alexander Graf wrote:
+/*
+ * Synchronize the timer IRQ state with the interrupt controller.
+ */
static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
{
int ret;
stru
On Fri, Sep 23, 2016 at 09:14:13AM +0200, Alexander Graf wrote:
>
>
> On 22.09.16 23:28, Christoffer Dall wrote:
> > On Thu, Sep 22, 2016 at 02:52:49PM +0200, Alexander Graf wrote:
> >> We have 2 modes for dealing with interrupts in the ARM world. We can either
> >> handle them all using hardware
On 23/09/2016 09:14, Alexander Graf wrote:
>>> +/*
>>> + * Synchronize the timer IRQ state with the interrupt controller.
>>> + */
>>> static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level)
>>> {
>>> int ret;
>>> struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
>>>
On 22.09.16 23:28, Christoffer Dall wrote:
> On Thu, Sep 22, 2016 at 02:52:49PM +0200, Alexander Graf wrote:
>> We have 2 modes for dealing with interrupts in the ARM world. We can either
>> handle them all using hardware acceleration through the vgic or we can
>> emulate
>> a gic in user space
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