[PATCH 3/3] KVM: arm/arm64: vgic: Kick VCPUs when queueing already pending IRQs

From: Shih-Wei Li In cases like IPI, we could be queueing an interrupt for a VCPU that is already running and is not about to exit, because the VCPU has entered the VM with the interrupt pending and would not trap on EOI'ing that interrupt. This could result to delays in

[PULL 0/3] KVM/ARM updates for v4.9-rc4

Paolo, Radim, Please find below the KVM/ARM updates for v4.9-rc4 (or later if we've already missed the boat). Thanks, M. The following changes since commit 07d9a380680d1c0eb51ef87ff2eab5c994949e69: Linux 4.9-rc2 (2016-10-23 17:10:14 -0700) are available in the git repository at:

[PATCH 2/3] KVM: arm/arm64: vgic: Prevent access to invalid SPIs

From: Andre Przywara In our VGIC implementation we limit the number of SPIs to a number that the userland application told us. Accordingly we limit the allocation of memory for virtual IRQs to that number. However in our MMIO dispatcher we didn't check if we ever access

Re: [PATCH v7 03/15] irq: move IRQ routing into irq.c

Hi Jean-Philippe, On 02/11/16 14:37, Jean-Philippe Brucker wrote: > On 20/07/16 18:04, Andre Przywara wrote: >> The current IRQ routing code in x86/irq.c is mostly implementing a >> generic KVM interface which other architectures may use too. >> Move the code to set up an MSI route into the

[PATCH v8 12/16] PCI: inject PCI device ID on MSI injection

The ITS emulation requires a unique device ID to be passed along the MSI payload when kvmtool wants to trigger an MSI in the guest. According to the proposed changes to the interface add the PCI bus/device/function triple to the structure passed with the ioctl. Check the respective capability

[PATCH v8 02/16] arm: use new phandle allocation functions

To refer to the GIC FDT node, we used to pass the GIC phandle to most of the functions dealing with FDT nodes. Since we now have a global phandle reference, use that to refer to the GIC handle in various places and get rid of the now unneeded parameter passing. Signed-off-by: Andre Przywara

[PATCH v8 14/16] extend GSI IRQ routing to take a device ID

For ITS emulation we need the device ID along with the MSI payload and doorbell address to identify an MSI, so we need to put it in the GSI IRQ routing table too. There is a per-VM capability by which the kernel signals the need for a device ID, so check this and put the device ID into the routing

[PATCH v8 09/16] arm: allow creation of an MSI register frame region

The GICv3 ITS expects a separate 64K page to hold ITS registers. Add a function to reserve such a page in the guest's I/O memory and use that for the ITS vGIC type. Signed-off-by: Andre Przywara --- arm/gic.c| 63

[PATCH v8 04/16] MSI-X: update GSI routing after changed MSI-X configuration

When we set up GSI routing to map MSIs to KVM's GSI numbers, we write the current device's MSI setup into the kernel routing table. However the device driver in the guest can use PCI configuration space accesses to change the MSI configuration (address and/or payload data). Whenever this happens

[PATCH v8 03/16] irq: move IRQ routing into irq.c

The current IRQ routing code in x86/irq.c is mostly implementing a generic KVM interface which other architectures may use too. Move the code to set up an MSI route into the generic irq.c file and guard it with the KVM_CAP_IRQ_ROUTING capability to return an error if the kernel does not support

[PATCH v8 07/16] update public Linux headers for GICv3 ITS emulation

The GICv3 ITS emulation brings some additions to the headers, so lets update kvmtool's version of the headers to Linux' v4.8-rc2. Signed-off-by: Andre Przywara --- arm/aarch32/include/asm/kvm.h | 4 ++-- arm/aarch64/include/asm/kvm.h | 2 ++ include/linux/kvm.h

[PATCH v8 05/16] virtio: fix endianness check for vhost support

Currently we deny any VHOST_* functionality if the architecture supports guests with different endianness than the host. Most of the time even on those architectures the endianness of guest and host are the same, though, so we are denying the glory of VHOST needlessly. Switch from compile time

[PATCH v8 16/16] arm: add support for vGICv3 and vITS

From: Vladimir Murzin KVM/arm got support for vGICv3 and vITS recently, so make use of it. Signed-off-by: Vladimir Murzin Signed-off-by: Andre Przywara --- arm/aarch32/arm-cpu.c | 2 +-

[PATCH v8 13/16] arm: setup SPI IRQ routing tables

Since we soon start using GSI routing on ARM platforms too, we have to setup the initial SPI routing table. Before the first call to KVM_SET_GSI_ROUTING, the kernel holds this table internally, but this is overwritten with the ioctl, so we have to explicitly set it up here. The routing is actually

[PATCH v8 11/16] add kvm__check_vm_capability

KVM capabilities can be per-VM, in this case the ioctl should be issued on the VM file descriptor, not on the system fd. Since this feature is guarded by a (system) capability itself, wrap the call into a function of its own. Signed-off-by: Andre Przywara ---

[PATCH v8 08/16] arm: gic: allow 32-bit compilation

The ARM GIC code is shared between ARM and arm64, though the header files from the Linux kernel are actually different, reflecting the different level of GIC emulation support between the two architectures. Since it is conceivable that ARM will gain GICv3 (and possibly ITS) emulation support too,

[PATCH v8 10/16] arm: FDT: create MSI controller DT node

The ARM GICv3 ITS requires a separate device tree node to describe the ITS. Add this as a child to the GIC interrupt controller node to let a guest discover and use the ITS if the user requests it. Since we now need to specify #address-cells for the GIC node, we have to add two zeroes to the

[PATCH v8 06/16] PCI: Only allocate IRQ routing entry when available

If we need to inject an MSI into the guest, we rely at the moment on a working GSI MSI routing functionality. However we can get away without IRQ routing, if the host supports MSI injection via the KVM_SIGNAL_MSI ioctl. So we try the GSI routing first, but if that fails due to a missing IRQ

[PATCH v8 01/16] FDT: introduce global phandle allocation

Allocating an FDT phandle (a unique identifier) using a static variable in a static inline function defined in a header file works only if all users are in the same source file. So trying to allocate a handle from two different compilation units fails. Introduce global phandle allocation and

[PATCH v8 00/16] kvmtool: arm: ITS emulation and GSI routing support

Hi, this series teaches kvmtool how to support KVM's ITS emulation. Also (as this is somewhat related and has been co-developed) it enables GSI routing for ARM/ARM64, which allows IRQFDs to be used, for instance to use vhost_net. At the moment this is dependent on the guest using the ITS

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

Hi Robert, On 03/11/2016 19:01, Robert Richter wrote: > Eric, > > On 21.10.16 11:05:01, Auger Eric wrote: >> On 21/10/2016 10:45, Marc Zyngier wrote: > >>> What is the failure syndrome? Do you see it crashing? Locking up? What >>> is the PC at that stage? >> No guest crash. the guest just locks

[PATCH v8 4/7] irqchip/gic-v3: Add missing system register definitions

From: Vijaya Kumar K Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers. Signed-off-by: Vijaya Kumar K --- include/linux/irqchip/arm-gic-v3.h | 43

[PATCH v8 2/7] arm/arm64: vgic: Add distributor and redistributor access

From: Vijaya Kumar K VGICv3 Distributor and Redistributor registers are accessed using KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_DIST_REGS with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls. These registers are accessed as 32-bit and cpu mpidr value

[PATCH v8 3/7] arm/arm64: vgic: Introduce find_reg_by_id()

From: Vijaya Kumar K In order to implement vGICv3 CPU interface access, we will need to perform table lookup of system registers. We would need both index_to_params() and find_reg() exported for that purpose, but instead we export a single function which combines them

[PATCH v8 6/7] arm/arm64: vgic: Implement VGICv3 CPU interface access

From: Vijaya Kumar K VGICv3 CPU interface registers are accessed using KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed as 64-bit. The cpu MPIDR value is passed along with register id. is used to identify the cpu for registers access. The version of VGIC

[PATCH v8 7/7] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl

From: Vijaya Kumar K Userspace requires to store and restore of line_level for level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO. Signed-off-by: Vijaya Kumar K --- arch/arm64/include/uapi/asm/kvm.h | 6 +

[PATCH v8 1/7] arm/arm64: vgic: Implement support for userspace access

From: Vijaya Kumar K Read and write of some registers like ISPENDR and ICPENDR from userspace requires special handling when compared to guest access for these registers. Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt for handling of ISPENDR, ICPENDR

[PATCH v8 5/7] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct

From: Vijaya Kumar K ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member variables to struct vmcr to support read and write of these fields. Also refactor vgic_set_vmcr and vgic_get_vmcr() code.

[PATCH v8 0/7] arm/arm64: vgic: Implement API for vGICv3 live migration

From: Vijaya Kumar K This patchset adds API for saving and restoring of VGICv3 registers to support live migration with new vgic feature. This API definition is as per version of VGICv3 specification