On 2016/12/6 19:47, Marc Zyngier wrote:
> On 06/12/16 06:41, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> Commit 50926d8(KVM: arm/arm64: The GIC is dead, long live the GIC)
>> removes the old vgic and commit 9097773(KVM: arm/arm64: vgic-new:
>> vgic_init: implement kvm_vgic_hyp_init) doesn't
On Tue, Dec 06, 2016 at 11:25:42AM +, Marc Zyngier wrote:
> On 05/12/16 09:32, Christoffer Dall wrote:
> > When the arch timer code fails to initialize (for example because the
> > memory mapped timer doesn't work, which is currently seen with the AEM
> > model), then KVM just continues happily
From: Christopher Covington
Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
even for the smallest delta of two subsequent reads.
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/pmu.c | 66 +++
This patch adds two new macros to support read/write operations of ARMv7
and ARMv8 system registers. As part of the change, xstr() is revised to
support variable arguments. With it, ARMv7 system register can be defined
with __ACCESS_CP15() or __ACCESS_CP15_64() depending if it is 32-bit or
64-bit.
To prepare for future support of ARMv8 system register, rename cp15.h file
to sysreg.h, with _ASMARM_CP15_H_ renamed to _ASMARM_SYSREG_H_ in header
file.
Signed-off-by: Wei Huang
---
arm/cstart.S | 2 +-
lib/arm/asm/{cp15.h => sysreg.h} | 6 +++---
2 files changed, 4 insertio
From: Christopher Covington
Calculate the numbers of cycles per instruction (CPI) implied by ARM
PMU cycle counter values. The code includes a strict checking facility
intended for the -icount option in TCG mode in the configuration file.
Signed-off-by: Christopher Covington
Signed-off-by: Wei
From: Christopher Covington
Beginning with a simple sanity check of the control register, add
a unit test for the ARM Performance Monitors Unit (PMU).
Signed-off-by: Christopher Covington
Signed-off-by: Wei Huang
---
arm/Makefile.common | 3 +-
arm/pmu.c | 93 ++
Changes from v13:
* Rename cp15.h to sysreg.h for ARMv7 and add a new file sysreg.h for ARMv8
* Add macros for read_sysreg() and write_sysreg(). CP15 registers can be
defined with __ACCESS_CP15() or __ACCESS_CP15_64(). sysreg.h (ARMv8) was
from Drew's GIC testing code, which can be leveraged wh
On 06/12/16 16:29, Christoffer Dall wrote:
> On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote:
>> The ARMv8 architecture allows the cycle counter to be configured
>> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
>> hence accessing PMCCFILTR_EL0. But it disallows the
On 05/12/16 08:09, Maninder Singh wrote:
> This patch corrects format specifier for printing 64 bit addresses.
>
> Signed-off-by: Maninder Singh
> Signed-off-by: Vaneet Narang
> ---
> arch/arm64/kernel/signal.c | 2 +-
> arch/arm64/kvm/sys_regs.c | 8 ++--
> arch/arm64/mm/fault.c |
On Tue, Dec 06, 2016 at 05:29:18PM +0100, Christoffer Dall wrote:
> On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote:
> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> > index 83037cd..3b7cfbd 100644
> > --- a/arch/arm64/kvm/hyp/switch.c
> > +++ b/arch/arm64/k
On 06/12/16 16:11, Christoffer Dall wrote:
> On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote:
>> This patch corrects format specifier for printing 64 bit addresses.
>>
>> Signed-off-by: Maninder Singh
>> Signed-off-by: Vaneet Narang
>> ---
>> arch/arm64/kernel/signal.c | 2 +-
>>
On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote:
> The ARMv8 architecture allows the cycle counter to be configured
> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
> hence accessing PMCCFILTR_EL0. But it disallows the use of
> PMSELR_EL0.SEL==0x1f to access the cyc
On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote:
> This patch corrects format specifier for printing 64 bit addresses.
>
> Signed-off-by: Maninder Singh
> Signed-off-by: Vaneet Narang
> ---
> arch/arm64/kernel/signal.c | 2 +-
> arch/arm64/kvm/sys_regs.c | 8 ++--
> arch/a
On 06/12/16 15:27, Will Deacon wrote:
> On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote:
>> The ARMv8 architecture allows the cycle counter to be configured
>> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
>> hence accessing PMCCFILTR_EL0. But it disallows the use
On Tue, Dec 06, 2016 at 03:26:37PM +, Catalin Marinas wrote:
> On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote:
> > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote:
> > > This patch corrects format specifier for printing 64 bit addresses.
> > >
> > > Signed-off-by: M
On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote:
> The ARMv8 architecture allows the cycle counter to be configured
> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
> hence accessing PMCCFILTR_EL0. But it disallows the use of
> PMSELR_EL0.SEL==0x1f to access the cyc
On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote:
> On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote:
> > This patch corrects format specifier for printing 64 bit addresses.
> >
> > Signed-off-by: Maninder Singh
> > Signed-off-by: Vaneet Narang
> > ---
> > arch/arm64/ke
The ARMv8 architecture allows the cycle counter to be configured
by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
hence accessing PMCCFILTR_EL0. But it disallows the use of
PMSELR_EL0.SEL==0x1f to access the cycle counter itself through
PMXEVCNTR_EL0.
Linux itself doesn't violate
On Tue, Dec 06, 2016 at 12:42:09PM +0100, Auger Eric wrote:
> Hi,
>
> On 28/11/2016 14:05, Christoffer Dall wrote:
> > On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kil...@gmail.com wrote:
> >> From: Vijaya Kumar K
> >>
> >> Read and write of some registers like ISPENDR and ICPENDR
> >> from us
On 06/12/16 13:50, Will Deacon wrote:
> On Fri, Dec 02, 2016 at 03:50:58PM +, Marc Zyngier wrote:
>> The ARMv8 architecture allows the cycle counter to be configured
>> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
>> hence accessing PMCCFILTR_EL0. But it disallows the use
On Tue, Dec 06, 2016 at 01:09:26PM +, Marc Zyngier wrote:
> On 06/12/16 12:16, Christoffer Dall wrote:
> > On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote:
> >> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote:
> >>> On 01/12/16 19:32, Jintack Lim wrote:
> Curr
Hi,
On 23/11/2016 14:01, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
> ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
>
> Signed-off-by: Vijaya Kumar K
> ---
> include/linux/irqchip/arm-gic-v3.h | 43
> ++
On Fri, Dec 02, 2016 at 03:50:58PM +, Marc Zyngier wrote:
> The ARMv8 architecture allows the cycle counter to be configured
> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
> hence accessing PMCCFILTR_EL0. But it disallows the use of
> PMSELR_EL0.SEL==0x1f to access the cyc
Hi Christoffer,
Thanks for the review.
On Tue, Dec 6, 2016 at 7:12 AM, Christoffer Dall
wrote:
> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote:
>> On 01/12/16 19:32, Jintack Lim wrote:
>> > Current KVM world switch code is unintentionally setting wrong bits to
>> > CNTHCTL_EL2 when
Hi Vijay,
On 23/11/2016 14:01, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> In order to implement vGICv3 CPU interface access, we will need to perform
> table lookup of system registers. We would need both index_to_params() and
> find_reg() exported for that purpose, but instead we ex
On Tue, Dec 6, 2016 at 6:17 AM, Marc Zyngier wrote:
> On 01/12/16 19:32, Jintack Lim wrote:
>> Current KVM world switch code is unintentionally setting wrong bits to
>> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
>> timer. Bit positions of CNTHCTL_EL2 are changing depen
Hi,
On 28/11/2016 14:08, Christoffer Dall wrote:
> On Wed, Nov 23, 2016 at 06:31:49PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> VGICv3 Distributor and Redistributor registers are accessed using
>> KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
>> with
On 06/12/16 12:16, Christoffer Dall wrote:
> On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote:
>> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote:
>>> On 01/12/16 19:32, Jintack Lim wrote:
Current KVM world switch code is unintentionally setting wrong bits to
On Thu, Dec 01, 2016 at 02:32:05PM -0500, Jintack Lim wrote:
> Current KVM world switch code is unintentionally setting wrong bits to
> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> timer. Bit positions of CNTHCTL_EL2 are changing depending on
> HCR_EL2.E2H bit. EL1PCEN
On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote:
> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote:
> > On 01/12/16 19:32, Jintack Lim wrote:
> > > Current KVM world switch code is unintentionally setting wrong bits to
> > > CNTHCTL_EL2 when E2H == 1, which may allow g
On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote:
> On 01/12/16 19:32, Jintack Lim wrote:
> > Current KVM world switch code is unintentionally setting wrong bits to
> > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> > timer. Bit positions of CNTHCTL_EL2 are ch
On 06/12/16 06:41, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Commit 50926d8(KVM: arm/arm64: The GIC is dead, long live the GIC)
> removes the old vgic and commit 9097773(KVM: arm/arm64: vgic-new:
> vgic_init: implement kvm_vgic_hyp_init) doesn't reset LRs for new-vgic
> when probing GIC. Thes
Hi,
On 28/11/2016 14:05, Christoffer Dall wrote:
> On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Read and write of some registers like ISPENDR and ICPENDR
>> from userspace requires special handling when compared to
>> guest access for these
On 06/12/16 06:41, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This is the corresponding part of commit d6400d7(KVM: arm/arm64:
> vgic-v2: Reset LRs at boot time) which is missed for new-vgic.
>
> Signed-off-by: Shannon Zhao
> ---
> virt/kvm/arm/vgic/vgic-v2.c | 11 +++
> 1 file chang
Hi Shannon,
On 06/12/16 06:41, Shannon Zhao wrote:
> From: Shannon Zhao
>
> This is the corresponding part of commit 0d98d00(arm64: KVM:
> vgic-v3: Reset LRs at boot time) which is missed for new-vgic.
>
> Signed-off-by: Shannon Zhao
> ---
> virt/kvm/arm/vgic/vgic-v3.c | 7 +++
> 1 file c
On 05/12/16 09:32, Christoffer Dall wrote:
> When the arch timer code fails to initialize (for example because the
> memory mapped timer doesn't work, which is currently seen with the AEM
> model), then KVM just continues happily with a final result that KVM
> eventually does a NULL pointer derefer
On Tue, Dec 06, 2016 at 11:14:41AM +, Andre Przywara wrote:
> Hi,
>
> On 06/12/16 09:48, Andrew Jones wrote:
> > On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
> >> This series proposes a framework to test the virtual ITS.
> >> This is based on Drew's v7 series [1]. The last patch
On 16/11/16 17:57, Andre Przywara wrote:
> The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that
> corresponds to an unimplemented CPU interface is RAZ/WI."
> Currently we allow the guest to write any value in there and it can
> read that back.
> Mask the written value with the p
On 01/12/16 19:32, Jintack Lim wrote:
> Current KVM world switch code is unintentionally setting wrong bits to
> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
> timer. Bit positions of CNTHCTL_EL2 are changing depending on
> HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st a
Hi,
On 06/12/16 09:48, Andrew Jones wrote:
> On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
>> This series proposes a framework to test the virtual ITS.
>> This is based on Drew's v7 series [1]. The last patch tests
>> several ITS commands (collection/device mapping, interrupt
>> tran
Hi Andre, Drew,
On 06/12/2016 10:32, Andre Przywara wrote:
> Hi,
>
> On 06/12/16 09:29, Andrew Jones wrote:
>> On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
>>> Add a new cpu_count field in gicv3_data indicating the
>>> number of redistributors. This will be useful for enumeration
>
On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
> This series proposes a framework to test the virtual ITS.
> This is based on Drew's v7 series [1]. The last patch tests
> several ITS commands (collection/device mapping, interrupt
> translation service entry creation and LPI trigger thr
Hi,
On 06/12/16 09:29, Andrew Jones wrote:
> On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
>> Add a new cpu_count field in gicv3_data indicating the
>> number of redistributors. This will be useful for enumeration
>> of their resources such as LPI pending tables.
>
> I'm fine with t
On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
> Add a new cpu_count field in gicv3_data indicating the
> number of redistributors. This will be useful for enumeration
> of their resources such as LPI pending tables.
I'm fine with the additional state, but just curious, will it
ever b
On Mon, Dec 05, 2016 at 10:46:34PM +0100, Eric Auger wrote:
> At the moment we just detect the presence of ITS as part of the
> GICv3 init routine and initialize its base address.
>
> Signed-off-by: Eric Auger
> ---
> arm/Makefile.common| 1 +
> lib/arm/asm/gic-v3-its.h | 22 +
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