On Wed, Jan 25, 2017 at 03:36:29PM +, Marc Zyngier wrote:
> When we fault in a page, we flush it to the PoC (Point of Coherency)
> if the faulting vcpu has its own caches off, so that it can observe
> the page we just brought it.
>
> But if the vcpu has its caches on, we skip that step. Bad th
On Wed, Jan 25, 2017 at 03:36:31PM +, Marc Zyngier wrote:
> KVM_MEMSLOT_INCOHERENT is not used anymore, as we've killed its
> only use in the arm/arm64 MMU code. Let's remove the last artifacts.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
__
On Wed, Jan 25, 2017 at 03:36:30PM +, Marc Zyngier wrote:
> Now that we unconditionally flush newly mapped pages to the PoC,
> there is no need to care about the "uncached" status of individual
> pages - they must all be visible all the way down.
>
> Signed-off-by: Marc Zyngier
Reviewed-by:
From: Vijaya Kumar K
ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
variables to struct vmcr to support read and write of these fields.
Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
Drop ICH_VMCR_CTLR_SHIFT a
From: Vijaya Kumar K
Read and write of some registers like ISPENDR and ICPENDR
from userspace requires special handling when compared to
guest access for these registers.
Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
for handling of ISPENDR, ICPENDR registers handling.
Add infrastr
From: Vijaya Kumar K
In order to implement vGICv3 CPU interface access, we will need to perform
table lookup of system registers. We would need both index_to_params() and
find_reg() exported for that purpose, but instead we export a single
function which combines them both.
Signed-off-by: Pavel
From: Vijaya Kumar K
VGICv3 Distributor and Redistributor registers are accessed using
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls.
These registers are accessed as 32-bit and cpu mpidr
value passed along with register
From: Vijaya Kumar K
This patchset adds API for saving and restoring
of VGICv3 registers to support live migration with new vgic feature.
This API definition is as per version of VGICv3 specification
Documentation/virtual/kvm/devices/arm-vgic-v3.txt
The patch 3 & 4 are picked from the Pavel's pr
From: Vijaya Kumar K
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K
Reviewed-by: Eric Auger
---
include/linux/irqchip/arm-gic-v3.h | 43 --
1 file changed, 41 i
From: Vijaya Kumar K
Userspace requires to store and restore of line_level for
level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
Signed-off-by: Vijaya Kumar K
---
arch/arm/include/uapi/asm/kvm.h | 6 +
arch/arm64/include/uapi/asm/kvm.h | 6 +
virt/kvm/arm/
From: Vijaya Kumar K
VGICv3 CPU interface registers are accessed using
KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
as 64-bit. The cpu MPIDR value is passed along with register id.
It is used to identify the cpu for registers access.
The VM that supports SEIs expect it on des
From: Vijaya Kumar K
Update error code returned for Invalid CPU interface register
value and access in AArch32 mode.
Signed-off-by: Vijaya Kumar K
---
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation
On Thu, Jan 26, 2017 at 07:50:52PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> Userspace requires to store and restore of line_level for
> level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
>
> Signed-off-by: Vijaya Kumar K
> ---
> arch/arm/include/uapi
On Thu, Jan 26, 2017 at 07:50:51PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> VGICv3 CPU interface registers are accessed using
> KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed
> as 64-bit. The cpu MPIDR value is passed along with register id.
> It is used t
On Thu, Jan 26, 2017 at 07:50:53PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> Update error code returned for Invalid CPU interface register
> value and access in AArch32 mode.
>
> Signed-off-by: Vijaya Kumar K
Acked-by: Christoffer Dall
___
Hi Vijaya,
On Thu, Jan 26, 2017 at 07:50:45PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> This patchset adds API for saving and restoring
> of VGICv3 registers to support live migration with new vgic feature.
> This API definition is as per version of VGICv3 specification
> D
On Thu, Jan 26, 2017 at 07:50:46PM +0530, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> Read and write of some registers like ISPENDR and ICPENDR
> from userspace requires special handling when compared to
> guest access for these registers.
>
> Refer to Documentation/virtual/kvm/device
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
---
includ
When scheduling a background timer, consider both of the virtual and
physical timer and pick the earliest expiration time.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c| 3 ++-
virt/kvm/arm/arch_timer.c | 55 ---
2 files changed, 44 insert
Now that we maintain the EL1 physical timer register states of VMs,
update the physical timer interrupt level along with the virtual one.
Note that the emulated EL1 physical timer is not mapped to any hardware
timer, so we call a proper vgic function.
Signed-off-by: Jintack Lim
---
virt/kvm/arm
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index d921d20..69f648b 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm
Set a background timer for the EL1 physical timer emulation while VMs
are running, so that VMs get the physical timer interrupts in a timely
manner.
Schedule the background timer on entry to the VM and cancel it on exit.
This would not have any performance impact to the guest OSes that
currently u
Make cntvoff per each timer context. This is helpful to abstract kvm
timer functions to work with timer context without considering timer
types (e.g. physical timer or virtual timer).
This also would pave the way for ever doing adjustments of the cntvoff
on a per-CPU basis if that should ever make
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 9 +++--
4 files changed, 25 ins
Now that we have a separate structure for timer context, make functions
general so that they can work with any timer context, not just the
virtual timer context. This does not change the virtual timer
functionality.
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c | 2 +-
include/kv
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c| 32 +---
include/kvm/arm_arch_timer.h | 2 ++
virt/kvm/arm/arch_timer.c| 2 +-
3
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 34 ++
The ARM architecture defines the EL1 physical timer and the virtual timer,
and it is reasonable for an OS to expect to be able to access both.
However, the current KVM implementation does not provide the EL1 physical
timer to VMs but terminates VMs on access to the timer.
This patch series enables
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