Hi Christoffer/Laszlo,
On 2017/3/30 1:44, Christoffer Dall wrote:
> On Wed, Mar 29, 2017 at 05:37:49PM +0200, Laszlo Ersek wrote:
>> On 03/29/17 16:48, Christoffer Dall wrote:
>>> On Wed, Mar 29, 2017 at 10:36:51PM +0800, gengdongjiu wrote:
2017-03-29 18:36 GMT+08:00, Achin Gupta
On Wed, Mar 29, 2017 at 2:06 PM, Christoffer Dall wrote:
> On Wed, Mar 29, 2017 at 01:51:19PM -0700, Radha Mohan wrote:
>> On Wed, Mar 29, 2017 at 11:56 AM, Christoffer Dall wrote:
>> > On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
>> >> On Tue,
On Wed, Mar 29, 2017 at 01:51:19PM -0700, Radha Mohan wrote:
> On Wed, Mar 29, 2017 at 11:56 AM, Christoffer Dall wrote:
> > On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
> >> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
> >> > Hi
On Wed, Mar 29, 2017 at 11:56 AM, Christoffer Dall wrote:
> On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
>> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
>> > Hi Radha,
>> >
>> > On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan
Hi Marc,
thanks for having a look!
On 29/03/17 09:30, Marc Zyngier wrote:
> On 02/02/17 16:32, Andre Przywara wrote:
>> If we need to inject an MSI into the guest, we rely at the moment on a
>> working GSI MSI routing functionality. However we can get away without
>> IRQ routing, if the host
On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
> > Hi Radha,
> >
> > On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan wrote:
> >> Hi,
> >> I am seeing an issue with qemu-system-aarch64 when using
On 29 March 2017 at 19:17, Radha Mohan wrote:
>> I will also try with qemu 2.8 and see.
>
> Same issue with 2.8.0 and 2.7.1 qemu version.
Thanks for checking -- good to know it's not a regression
on the QEMU side. (If you can soft-lockup the host it's
clearly a host kernel
On Tue, Mar 28, 2017 at 1:24 PM, Radha Mohan wrote:
> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
>> Hi Radha,
>>
>> On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan wrote:
>>> Hi,
>>> I am seeing an issue with qemu-system-aarch64 when
On 03/29/17 16:48, Christoffer Dall wrote:
> On Wed, Mar 29, 2017 at 10:36:51PM +0800, gengdongjiu wrote:
>> 2017-03-29 18:36 GMT+08:00, Achin Gupta :
>>> Qemu is essentially fulfilling the role of secure firmware at the
>>> EL2/EL1 interface (as discussed with Christoffer
On Wed, Mar 29, 2017 at 10:36:51PM +0800, gengdongjiu wrote:
> Hi Achin,
> Thanks for your mail and answer.
>
> 2017-03-29 18:36 GMT+08:00, Achin Gupta :
> > Hi gengdongjiu,
> >
> > On Wed, Mar 29, 2017 at 05:36:37PM +0800, gengdongjiu wrote:
> >>
> >> Hi
Hi Achin,
Thanks for your mail and answer.
2017-03-29 18:36 GMT+08:00, Achin Gupta :
> Hi gengdongjiu,
>
> On Wed, Mar 29, 2017 at 05:36:37PM +0800, gengdongjiu wrote:
>>
>> Hi Laszlo/Biesheuvel/Qemu developer,
>>
>>Now I encounter a issue and want to consult with you
On Wed, Mar 29, 2017 at 03:36:59PM +0200, Laszlo Ersek wrote:
> On 03/29/17 14:51, Michael S. Tsirkin wrote:
> > On Wed, Mar 29, 2017 at 01:58:29PM +0200, Laszlo Ersek wrote:
> >> (8) When QEMU gets SIGBUS from the kernel -- I hope that's going to come
> >> through a signalfd -- QEMU can format
On 03/29/17 14:51, Michael S. Tsirkin wrote:
> On Wed, Mar 29, 2017 at 01:58:29PM +0200, Laszlo Ersek wrote:
>> (8) When QEMU gets SIGBUS from the kernel -- I hope that's going to come
>> through a signalfd -- QEMU can format the CPER right into guest memory,
>> and then inject whatever interrupt
On Wed, Mar 29, 2017 at 01:58:29PM +0200, Laszlo Ersek wrote:
> (8) When QEMU gets SIGBUS from the kernel -- I hope that's going to come
> through a signalfd -- QEMU can format the CPER right into guest memory,
> and then inject whatever interrupt (or assert whatever GPIO line) is
> necessary for
(This ought to be one of the longest address lists I've ever seen :)
Thanks for the CC. I'm glad Shannon is already on the CC list. For good
measure, I'm adding MST and Igor.)
On 03/29/17 12:36, Achin Gupta wrote:
> Hi gengdongjiu,
>
> On Wed, Mar 29, 2017 at 05:36:37PM +0800, gengdongjiu wrote:
Hi gengdongjiu,
On Wed, Mar 29, 2017 at 05:36:37PM +0800, gengdongjiu wrote:
>
> Hi Laszlo/Biesheuvel/Qemu developer,
>
>Now I encounter a issue and want to consult with you in ARM64 platform, as
> described below:
>
>when guest OS happen synchronous or asynchronous abort, kvm needs to
On 02/02/17 16:32, Andre Przywara wrote:
> When we set up GSI routing to map MSIs to KVM's GSI numbers, we
> write the current device's MSI setup into the kernel routing table.
> However the device driver in the guest can use PCI configuration space
> accesses to change the MSI configuration
On Wed, Mar 29, 2017 at 09:41:47AM +0100, Will Deacon wrote:
> On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote:
> > On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote:
> > > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote:
> > > I think it would make sense
Hi Laszlo/Biesheuvel/Qemu developer,
Now I encounter a issue and want to consult with you in ARM64 platform, as
described below:
when guest OS happen synchronous or asynchronous abort, kvm needs to send
the error address to Qemu or UEFI through sigbus to dynamically generate APEI
On 02/02/17 16:32, Andre Przywara wrote:
> Hi,
>
> an update to the ITS emulation series for kvmtool.
> I reworked the phandle allocation by actually removing and replacing it
> with some simple, static assignments. That definitely fits kvmtool's
> needs today, where the GIC and the PCI
On 02/02/17 16:32, Andre Przywara wrote:
> For ITS emulation we need the device ID along with the MSI payload
> and doorbell address to identify an MSI, so we need to put it in the
> GSI IRQ routing table too.
> There is a per-VM capability by which the kernel signals the need for
> a device ID,
On 02/02/17 16:32, Andre Przywara wrote:
> The ITS emulation requires a unique device ID to be passed along the
> MSI payload when kvmtool wants to trigger an MSI in the guest.
> According to the proposed changes to the interface add the PCI
> bus/device/function triple to the structure passed
On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote:
> On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote:
> > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote:
> > > On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote:
> > > > On Fri, Mar 10, 2017 at
On 02/02/17 16:32, Andre Przywara wrote:
> The GICv3 ITS expects a separate 64K page to hold ITS registers.
> Add a function to reserve such a page in the guest's I/O memory and
> use that for the ITS vGIC type.
Strictly speaking, this should be a 128kB region, including the page
containing
On 02/02/17 16:32, Andre Przywara wrote:
> If we need to inject an MSI into the guest, we rely at the moment on a
> working GSI MSI routing functionality. However we can get away without
> IRQ routing, if the host supports MSI injection via the KVM_SIGNAL_MSI
> ioctl.
> So we try the GSI routing
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