On Mon, Oct 16, 2017 at 02:35:47PM -0700, Roy Franz (Cavium) wrote:
> On Mon, Oct 9, 2017 at 8:20 AM, Marc Zyngier wrote:
> > As we're about to introduce opportunistic invalidation of the icache,
> > let's split dcache and icache flushing.
> >
> > Signed-off-by: Marc Zyngier
> > ---
> > arch/arm
On Mon, Oct 9, 2017 at 8:20 AM, Marc Zyngier wrote:
> As we're about to introduce opportunistic invalidation of the icache,
> let's split dcache and icache flushing.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm/include/asm/kvm_mmu.h | 60
>
> arch/
On Mon, Oct 09, 2017 at 04:20:22PM +0100, Marc Zyngier wrote:
> It was recently reported that on a VM restore, we seem to spend a
> disproportionate amount of time invalidation the icache. This is
> partially due to some HW behaviour, but also because we're being a bit
> dumb and are invalidating t
On Tue, Sep 26, 2017 at 11:14:52PM +0200, Florent Revest wrote:
> On Thu, 2017-08-31 at 11:26 +0200, Christoffer Dall wrote:
> > I wonder if this should be split into two series; one that sets up
> > anything you may need from KVM, and another one that uses that for
> > UEFI.
> >
> > There's a lot
On Tue, Sep 26, 2017 at 11:14:45PM +0200, Florent Revest wrote:
> On Thu, 2017-08-31 at 11:23 +0200, Christoffer Dall wrote:
> > > diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> > > index 2ea21da..1d2d3df 100644
> > > --- a/virt/kvm/arm/mmu.c
> > > +++ b/virt/kvm/arm/mmu.c
> > > @@ -772,6 +
On Mon, Oct 09, 2017 at 04:20:24PM +0100, Marc Zyngier wrote:
> We currently tightly couple dcache clean with icache invalidation,
> but KVM could do without the initial flush to PoU, as we've
> already flushed things to PoC.
>
> Let's introduce invalidate_icache_range which is limited to
> invali
On Mon, Oct 09, 2017 at 04:20:31PM +0100, Marc Zyngier wrote:
> kvm_hyp.h has an odd dependency on kvm_mmu.h, which makes the
> opposite inclusion impossible. Let's start with breaking that
> useless dependency.
>
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
> ---
> arch/arm/inclu
On Mon, Oct 09, 2017 at 04:20:30PM +0100, Marc Zyngier wrote:
> The vcpu parameter isn't used for anything, and gets in the way of
> further cleanups. Let's get rid of it.
>
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
> ---
> arch/arm/include/asm/kvm_mmu.h | 6 ++
> arch/a
On Mon, Oct 09, 2017 at 04:20:28PM +0100, Marc Zyngier wrote:
> The only case where we actually need to perform a dache maintenance
> is when we map the page for the first time, and subsequent permission
> faults do not require cache maintenance. Let's make it conditional
> on not being a permissio
On Mon, Oct 09, 2017 at 04:20:29PM +0100, Marc Zyngier wrote:
> So far, we loose the Exec property whenever we take permission
> faults, as we always reconstruct the PTE/PMD from scratch. This
> can be counter productive as we can end-up with the following
> fault sequence:
>
> X -> RO -> RO
On Mon, Oct 09, 2017 at 04:20:27PM +0100, Marc Zyngier wrote:
> We've so far eagerly invalidated the icache, no matter how
> the page was faulted in (data or prefetch abort).
>
> But we can easily track execution by setting the XN bits
> in the S2 page tables, get the prefetch abort at HYP and
> p
On Mon, Oct 09, 2017 at 04:20:26PM +0100, Marc Zyngier wrote:
> As we're about to make S2 page-tables eXecute Never by default,
> add the required bits for both PMDs and PTEs.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Christoffer Dall
> ---
> arch/arm64/include/asm/pgtable-hwdef.h | 2 ++
>
On Mon, Oct 09, 2017 at 04:20:23PM +0100, Marc Zyngier wrote:
> As we're about to introduce opportunistic invalidation of the icache,
> let's split dcache and icache flushing.
I'm a little confused abut the naming of these functions now,
because where I believe the current function ensures coheren
On Mon, Oct 09, 2017 at 04:20:32PM +0100, Marc Zyngier wrote:
> We currently have no less than three implementations for the
> "flush to PoC" code. Let standardize on a single one. This
> requires a bit of unpleasant moving around, and relies on
> __kvm_flush_dcache_pte and co being #defines so tha
On Mon, Oct 16, 2017 at 04:10:01PM +, gengdongjiu wrote:
> Hi Marc,
>
> >
> > Please also update the 32bit code accordingly, as it looks broken too.
>
> I have updated the 32 bit code according, in my hand, there is no arm32 host
> environment,
> So there is no method to verify it in the ar
Hi gengdongjiu,
On 15/10/17 17:09, gengdongjiu wrote:
>> On 13/10/17 10:25, gengdongjiu wrote:
>>> In my first version patch [2], It sets the virtual ESR in the KVM, but
>>> Marc and other people disagree that[3][4],and propose to set its value
>>> and injection by userspace(when RAS is enabled).
Hi gengdongjiu,
On 16/10/17 04:17, gengdongjiu wrote:
>> In fact I have below method for that, what do you think about that?
>>
>> 1. If there is no RAS, old method, directly inject virtual SError, not need
>> to specify ESR, as shown in the [1]
>> 2. If there is RAS, KVM set "the kvm_run" gues
On 16/10/17 17:55, Dave Martin wrote:
On Mon, Oct 16, 2017 at 05:47:16PM +0100, Suzuki K Poulose wrote:
On 16/10/17 17:44, Dave Martin wrote:
On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
On 16/10/17 16:46, Dave Martin wrote:
On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuk
On Mon, Oct 16, 2017 at 05:47:16PM +0100, Suzuki K Poulose wrote:
> On 16/10/17 17:44, Dave Martin wrote:
> >On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
> >>On 16/10/17 16:46, Dave Martin wrote:
> >>>On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
> On 10
On 16/10/17 17:44, Dave Martin wrote:
On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
On 16/10/17 16:46, Dave Martin wrote:
On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
On 10/10/17 19:38, Dave Martin wrote:
[...]
@@ -670,6 +689,14 @@ void update_cpu_f
On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
> On 16/10/17 16:46, Dave Martin wrote:
> >On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
> >>On 10/10/17 19:38, Dave Martin wrote:
[...]
> >>>@@ -670,6 +689,14 @@ void update_cpu_features(int cpu,
> >>>
On 16/10/17 16:46, Dave Martin wrote:
On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
On 10/10/17 19:38, Dave Martin wrote:
This patch uses the cpufeatures framework to determine common SVE
capabilities and vector lengths, and configures the runtime SVE
support code appropriat
Hi Marc,
>
> Please also update the 32bit code accordingly, as it looks broken too.
I have updated the 32 bit code according, in my hand, there is no arm32 host
environment,
So there is no method to verify it in the arm32 host, only verify the patch in
the arm64 host.
Anyway I firstly send th
When a exception is trapped to EL2, hardware uses ELR_ELx to hold
the current fault instruction address. If KVM wants to inject a
abort to 32 bit guest, it needs to set the LR register for the
guest to emulate this abort happened in the guest. Because ARM32
architecture is pipelined execution, so
On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
> On 10/10/17 19:38, Dave Martin wrote:
> >This patch uses the cpufeatures framework to determine common SVE
> >capabilities and vector lengths, and configures the runtime SVE
> >support code appropriately.
> >
> >ZCR_ELx is not real
On reset we clear the valid bits of GITS_CBASER and GITS_BASER.
We also clear command queue registers and free the cache (device,
collection, and lpi lists).
Signed-off-by: Eric Auger
Reviewed-by: Christoffer Dall
---
v2 -> v3:
- added Christoffer's R-b
---
arch/arm/include/uapi/asm/kvm.h |
From: wanghaibin
We create 2 new functions that frees the device and
collection lists. this is currently called by vgic_its_destroy()
and we will add other callers in subsequent patches.
We also remove the check on its->device_list.next as it looks
unnecessary. Indeed, the device list always is
At the moment we don't properly check the GITS_BASER.Valid
bit before saving the collection and device tables.
On vgic_its_save_collection_table() we use the GITS_BASER gpa
field whereas the Valid bit should be used.
On vgic_its_save_device_tables() there is no check. This can
cause various bugs,
At the moment, the in-kernel emulated ITS is not properly reset.
On guest restart/reset some registers keep their old values and
internal structures like device, ITE, and collection lists are not
freed.
This may lead to various bugs. Among them, we can have incorrect state
backup or failure when s
When the GITS_BASER.Valid gets cleared, the data structures in
guest RAM are not valid anymore. The device, collection
and LPI lists stored in the in-kernel ITS represent the same
information in some form of cache. So let's void the cache.
Signed-off-by: Eric Auger
---
v2 -> v3:
- add a comment
At the moment vgic_its_process_commands() does not
check the CBASER is valid before processing any command.
Let's fix that.
Also rename cbaser local variable into cbaser_pa to avoid
any confusion with the full register.
Signed-off-by: Eric Auger
---
virt/kvm/arm/vgic/vgic-its.c | 13 ---
This series fixes various bugs observed when saving/restoring the
ITS state before the guest writes the ITS registers (on first boot or
after reset/reboot).
This is a follow up of Wanghaibin's series [1] plus additional
patches following additional code review. It also proposes one
ITS reset imple
At the moment the device table save() returns -EINVAL if
vgic_its_check_id() fails to return the gpa of the entry
associated to the device/collection id. Let vgic_its_check_id()
return an int instead of a bool and return a more precised
error value:
- EINVAL in case the id is out of range
- EFAULT
In case the device table save fails, we currently do not
attempt to save the collection table. However it may
happen that the device table fails because the structures
in memory are inconsistent with device GITS_BASER however
this does not mean collection backup can't and shouldn't
be performed. Sa
vgic_its_restore_cte returns +1 if the collection table entry
is valid and properly decoded. As a consequence, if the
collection table is fully filled with valid data that are
decoded without error, vgic_its_restore_collection_table()
returns +1. This is wrong.
Let's use the standard C convention
The spec says it is UNPREDICTABLE to enable the ITS
if any of the following conditions are true:
- GITS_CBASER.Valid == 0.
- GITS_BASER.Valid == 0, for any GITS_BASER register
where the Type field indicates Device.
- GITS_BASER.Valid == 0, for any GITS_BASER register
where the Type field indic
AT the moment if ITT only contains invalid entries,
vgic_its_restore_itt returns 1 and this is considered as
an an error in vgic_its_restore_dte.
Also in case the device table only contains invalid entries,
the table restore fails and this is not correct.
This patch fully revisits the errror hand
On Fri, Sep 22, 2017 at 07:26:11PM +0100, James Morse wrote:
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> index f24bfb2b9a2d..466b949474df 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -88,6 +88,7 @@ enum cpuhp_state {
> CPUHP_AP
Hi James,
>
>> Today I added the support to do some minimal emulation for
>> RAS-Error-Record registers, thanks
>> for the good suggestion.
>
> Where can I find this patch?
> I'd like to repost it as part of the SError_rework/RAS/IESB series: this is
> one
> of the bits KVM needs but I didn't touc
On Fri, Sep 22, 2017 at 07:26:10PM +0100, James Morse wrote:
> diff --git a/arch/arm64/include/asm/sdei.h b/arch/arm64/include/asm/sdei.h
> new file mode 100644
> index ..ed329e01a301
> --- /dev/null
> +++ b/arch/arm64/include/asm/sdei.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2017
Hi gengdongjiu,
On 14/09/17 12:12, gengdongjiu wrote:
> On 2017/9/8 0:31, James Morse wrote:
>> KVM already handles external aborts from lower exception levels, no more work
>> needs doing for TEA.
> If it is firmware first solution, that is SCR_EL3.EA=1, all SError interrupt
> and synchronous Ex
On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote:
> diff --git a/arch/arm64/include/asm/processor.h
> b/arch/arm64/include/asm/processor.h
> index 29adab8138c3..8f2d0f7d193b 100644
> --- a/arch/arm64/include/asm/processor.h
> +++ b/arch/arm64/include/asm/processor.h
> @@ -193,5 +193,6 @
On Fri, Oct 13, 2017 at 05:50:45PM +0100, James Morse wrote:
> Hi Catalin,
>
> On 13/10/17 16:31, Catalin Marinas wrote:
> > On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote:
> >> diff --git a/arch/arm64/kernel/cpufeature.c
> >> b/arch/arm64/kernel/cpufeature.c
> >> index cd52d365d1f0.
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