Re: [PATCH v6 2/9] KVM: arm/arm64: vgic-its: Fix vgic_its_restore_collection_table returned value

On Thu, Oct 26, 2017 at 05:23:04PM +0200, Eric Auger wrote: > vgic_its_restore_cte returns +1 if the collection table entry > is valid and properly decoded. As a consequence, if the > collection table is fully filled with valid data that are > decoded without error,

Re: [PATCH v4 17/21] KVM: arm64: Save ESR_EL2 on guest SError

Hi Marc, On 31/10/17 05:47, Marc Zyngier wrote: > On Tue, Oct 31 2017 at 4:26:01 am GMT, Marc Zyngier > wrote: >> On Thu, Oct 19 2017 at 4:58:03 pm BST, James Morse >> wrote: >>> When we exit a guest due to an SError the vcpu fault info isn't

[PATCH 15/13] firmware: arm_sdei: move the frozen flag under the spinlock

dpm_suspend() calls the freeze/thaw callbacks for hibernate before disable_non_bootcpus() takes down secondaries. This leads to a fun race where the freeze/thaw callbacks reset the SDEI interface (as we may be restoring a kernel with a different layout due to KASLR), then the cpu-hotplug

Re: [PATCH v4 11/13] firmware: arm_sdei: add support for CPU private events

Hi Will, On 24/10/17 18:34, James Morse wrote: > On 18/10/17 18:19, Will Deacon wrote: >> On Tue, Oct 17, 2017 at 06:44:30PM +0100, James Morse wrote: >>> Private SDE events are per-cpu, and need to be registered and enabled >>> on each CPU. >>> >>> Hide this detail from the caller by adapting

Re: [PATCH v4 00/21] SError rework + RAS for firmware first support

Hi guys, On 31/10/17 10:08, Will Deacon wrote: > On Tue, Oct 31, 2017 at 07:35:35AM +0100, Christoffer Dall wrote: >> On Thu, Oct 19, 2017 at 03:57:46PM +0100, James Morse wrote: >>> The aim of this series is to enable IESB and add ESB-instructions to let us >>> kick any pending RAS errors into

Re: [PATCH v5 15/30] arm64/sve: Signal handling support

On Tue, Oct 31, 2017 at 03:51:07PM +, Dave P Martin wrote: > This patch implements support for saving and restoring the SVE > registers around signals. > > A fixed-size header struct sve_context is always included in the > signal frame encoding the thread's vector length at the time of >

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

> > On 01/11/17 12:54, gengdongjiu wrote: > > Hi Robin, > > > > On 2017/11/1 19:24, Robin Murphy wrote: > >>> + esb > >>> +alternative_else_nop_endif > >>> +1: > >>> + .endm > >> Having a branch in here is pretty horrible, and furthermore using > >> label number 1 has a pretty high chance of

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

On Wed, Nov 01, 2017 at 08:54:44PM +0800, gengdongjiu wrote: > On 2017/11/1 19:24, Robin Murphy wrote: > >> + esb > >> +alternative_else_nop_endif > >> +1: > >> + .endm > > Having a branch in here is pretty horrible, and furthermore using label > > number 1 has a pretty high chance of subtly

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

On 01/11/17 12:54, gengdongjiu wrote: > Hi Robin, > > On 2017/11/1 19:24, Robin Murphy wrote: >>> + esb >>> +alternative_else_nop_endif >>> +1: >>> + .endm >> Having a branch in here is pretty horrible, and furthermore using label >> number 1 has a pretty high chance of subtly breaking code

Re: [PATCH v5 01/30] regset: Add support for dynamically sized regsets

On Wed, Nov 01, 2017 at 11:42:29AM +, Catalin Marinas wrote: > On Tue, Oct 31, 2017 at 03:50:53PM +, Dave P Martin wrote: > > Currently the regset API doesn't allow for the possibility that > > regsets (or at least, the amount of meaningful data in a regset) > > may change in size. > > >

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

Hi Robin, On 2017/11/1 19:24, Robin Murphy wrote: >> +esb >> +alternative_else_nop_endif >> +1: >> +.endm > Having a branch in here is pretty horrible, and furthermore using label > number 1 has a pretty high chance of subtly breaking code where this > macro is inserted. > > Can we not

Re: [PATCH v1 0/3] manually add Error Synchronization Barrier at exception handler entry and exit

On 2017/11/1 19:32, James Morse wrote: >> RAS for firmware first support". In Huawei's platform, we do not >> support IESB, so software needs to insert that. > Surely you don't implement it because your CPU doesn't need it. Can > unrecoverable errors really cross an exception without becoming an

Re: [PATCH v5 02/30] arm64: fpsimd: Correctly annotate exception helpers called from asm

On Tue, Oct 31, 2017 at 03:50:54PM +, Dave P Martin wrote: > A couple of FPSIMD exception handling functions that are called > from entry.S are currently not annotated as such. > > This is not a big deal since asmlinkage does nothing on arm/arm64, > but fixing the annotations is more

Re: [PATCH v5 03/30] arm64: signal: Verify extra data is user-readable in sys_rt_sigreturn

On Tue, Oct 31, 2017 at 03:50:55PM +, Dave P Martin wrote: > Currently sys_rt_sigreturn() verifies that the base sigframe is > readable, but no similar check is performed on the extra data to > which an extra_context record points. > > This matters because the extra data will be read with the

Re: [PATCH v5 01/30] regset: Add support for dynamically sized regsets

On Tue, Oct 31, 2017 at 03:50:53PM +, Dave P Martin wrote: > Currently the regset API doesn't allow for the possibility that > regsets (or at least, the amount of meaningful data in a regset) > may change in size. > > In particular, this results in useless padding being added to > coredumps

Re: [PATCH v1 0/3] manually add Error Synchronization Barrier at exception handler entry and exit

Hi Dongjiu Geng, On 01/11/17 19:14, Dongjiu Geng wrote: > Some hardware platform can support RAS Extension, but not support IESB, > such as Huawei's platform, so software need to insert Synchronization Barrier > operations at exception handler entry. > > This series patches are based on James's

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

On 01/11/17 19:14, Dongjiu Geng wrote: > ARMv8.2 adds a control bit to each SCTLR_ELx to insert implicit > Error Synchronization Barrier(IESB) operations at exception handler entry > and exit. But not all hardware platform which support RAS Extension > can support IESB. So for this case, software

Re: [PATCH v1 0/3] manually add Error Synchronization Barrier at exception handler entry and exit

On 01/11/17 19:14, Dongjiu Geng wrote: > Some hardware platform can support RAS Extension, but not support IESB, > such as Huawei's platform, so software need to insert Synchronization Barrier > operations at exception handler entry. > > This series patches are based on James's series patches

[PATCH v1 1/3] arm64: add a macro for SError synchronization

ARMv8.2 adds a control bit to each SCTLR_ELx to insert implicit Error Synchronization Barrier(IESB) operations at exception handler entry and exit. But not all hardware platform which support RAS Extension can support IESB. So for this case, software needs to manually insert Error Synchronization

[PATCH v1 3/3] KVM: arm64: add ESB in exception handler entry and exit.

Some hardware platform can support RAS Extension instead of support IESB, so software need to insert Synchronization Barrier operations at exception handler entry and exit. In the __guest_exit(), it added a ESB instruction, but can not cover the path which is not guest exit. For example, if EL1

[PATCH v1 2/3] arm64: add error synchronization barrier in kernel_entry/kernel_exit

If taking an exception from or return to user space, insert a Error Synchronization Barrier(ESB) to isolate the error. If a user space process is pending a SError, when enter to kernel, the SError will be immediately synchronized in the handler entry. Otherwise if kernel space is pending a

Re: [PATCH v5 04/30] arm64: KVM: Hide unsupported AArch64 CPU features from guests

On Wed, Nov 01, 2017 at 05:47:29AM +0100, Christoffer Dall wrote: > On Tue, Oct 31, 2017 at 03:50:56PM +, Dave Martin wrote: > > Currently, a guest kernel sees the true CPU feature registers > > (ID_*_EL1) when it reads them using MRS instructions. This means > > that the guest may observe

Re: [PATCH v3 6/9] KVM: arm/arm64: Limit icache invalidation to prefetch aborts

On Mon, Oct 23, 2017 at 05:11:19PM +0100, Marc Zyngier wrote: > diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c > index 2174244f6317..0417c8e2a81c 100644 > --- a/virt/kvm/arm/mmu.c > +++ b/virt/kvm/arm/mmu.c > @@ -1292,7 +1292,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, >