On Tue, Feb 13, 2018 at 11:41:16AM +0100, Jérémy Fanguède wrote:
> Set the handlers to emulate read and write operations for CNTP_CTL,
> CNTP_CVAL and CNTP_TVAL registers in such a way that VMs can use the
> physical timer.
>
> Signed-off-by: Jérémy Fanguède
> ---
>
> This patch is the equivalen
On Thu, Feb 15, 2018 at 01:11:02PM +, Marc Zyngier wrote:
> On 15/01/18 11:47, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:23PM +, Marc Zyngier wrote:
> >> So far, we're using a complicated sequence of alternatives to
> >> patch the kernel/hyp VA mask on non-VHE, and NOP out t
On Thu, Feb 15, 2018 at 01:22:56PM +, Marc Zyngier wrote:
> On 15/01/18 15:36, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:25PM +, Marc Zyngier wrote:
> >> kvm_vgic_global_state is part of the read-only section, and is
> >> usually accessed using a PC-relative address generati
On Thu, Feb 15, 2018 at 01:52:05PM +, Marc Zyngier wrote:
> On 18/01/18 14:39, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:29PM +, Marc Zyngier wrote:
> >> We so far mapped our HYP IO (which is essencially the GICv2 control
> >> registers) using the same method as for memory.
On Thu, Feb 15, 2018 at 03:32:52PM +, Marc Zyngier wrote:
> On 18/01/18 20:28, Christoffer Dall wrote:
> > On Thu, Jan 04, 2018 at 06:43:33PM +, Marc Zyngier wrote:
> >> The main idea behind randomising the EL2 VA is that we usually have
> >> a few spare bits between the most significant bi
On 16/02/18 09:05, Christoffer Dall wrote:
> On Thu, Feb 15, 2018 at 01:22:56PM +, Marc Zyngier wrote:
>> On 15/01/18 15:36, Christoffer Dall wrote:
>>> On Thu, Jan 04, 2018 at 06:43:25PM +, Marc Zyngier wrote:
kvm_vgic_global_state is part of the read-only section, and is
usually
On 16/02/18 09:25, Christoffer Dall wrote:
> On Thu, Feb 15, 2018 at 01:52:05PM +, Marc Zyngier wrote:
>> On 18/01/18 14:39, Christoffer Dall wrote:
>>> On Thu, Jan 04, 2018 at 06:43:29PM +, Marc Zyngier wrote:
We so far mapped our HYP IO (which is essencially the GICv2 control
re
This series attempts to integrate KVM's FPSIMD context handling more
closely with the host, so that we can take advantage of better
knowledge about when the FPSIMD registers are live and whose data they
contain.
These patches are based on:
git://git.kernel.org/pub/scm/linux/kernel/git/cdall/linux
To make the lazt FPSIMD context switch trap code easier to hack on,
this patch converts it to C.
This is not amazingly efficient, but the trap should typically only
be taken once per host context switch.
Signed-off-by: Dave Martin
---
arch/arm64/kvm/hyp/entry.S | 57 +--
Currently, KVM doesn't know how host tasks interact with the cpu
FPSIMD regs, and the host doesn't knoe how vcpus interact with the
regs. As a result, KVM must currently switch the FPSIMD state
rather defensively in order to avoid anybody's state getting
corrupted: in particular, the host and gues
Oops, forgot to post this patch that goes before patch 1 in the series.
--8<--
Expose an interface for associating an FPSIMD context with a CPU and
checking the association, for use by KVM.
Signed-off-by: Dave Martin
---
arch/arm64/include/asm/fpsimd.h | 5 +
arch/arm64/kernel/fpsimd.c
Two point of unification cache maintenance operations 'DC CVAU' and
'IC IVAU' are optional for implementors as per ARMv8 specification.
This patch parses the updated CTR_EL0 register definition and adds
the required changes to skip POU operations if the hardware reports
CTR_EL0.IDC and/or CTR_EL0.I
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