Hi, Eric, Marc and Christoffer,
On Thu, 2018-03-08 at 19:12 +0100, Auger Eric wrote:
> Hi Marc, Christoffer,
>
> On 08/03/18 18:28, Marc Zyngier wrote:
> >
> > On Thu, 08 Mar 2018 16:19:00 +,
> > Christoffer Dall wrote:
> > >
> > >
> > > On Thu, Mar 08, 2018 at 11:54:27AM +, Marc
Hi Marc, Christoffer,
On 08/03/18 18:28, Marc Zyngier wrote:
> On Thu, 08 Mar 2018 16:19:00 +,
> Christoffer Dall wrote:
>>
>> On Thu, Mar 08, 2018 at 11:54:27AM +, Marc Zyngier wrote:
>>> On 08/03/18 09:49, Marc Zyngier wrote:
[updated Christoffer's email address]
Hi
On Thu, Mar 01, 2018 at 03:55:37PM +, Marc Zyngier wrote:
> We're now ready to map our vectors in weird and wonderful locations.
> On enabling ARM64_HARDEN_EL2_VECTORS, a vector slots gets allocated
> if this hasn't been already done via ARM64_HARDEN_BRANCH_PREDICTOR
> and gets mapped outside
On Thu, 08 Mar 2018 16:19:00 +,
Christoffer Dall wrote:
>
> On Thu, Mar 08, 2018 at 11:54:27AM +, Marc Zyngier wrote:
> > On 08/03/18 09:49, Marc Zyngier wrote:
> > > [updated Christoffer's email address]
> > >
> > > Hi Shunyong,
> > >
> > > On 08/03/18 07:01, Shunyong Yang wrote:
> >
On Thu, 08 Mar 2018 16:02:42 +,
Christoffer Dall wrote:
>
> On Thu, Mar 08, 2018 at 10:19:49AM +, Marc Zyngier wrote:
> > On 07/03/18 23:34, Christoffer Dall wrote:
> > > On Wed, Mar 7, 2018 at 12:40 PM, Marc Zyngier
> > > wrote:
> > >> The vgic code is trying to
On Thu, Mar 08, 2018 at 11:54:27AM +, Marc Zyngier wrote:
> On 08/03/18 09:49, Marc Zyngier wrote:
> > [updated Christoffer's email address]
> >
> > Hi Shunyong,
> >
> > On 08/03/18 07:01, Shunyong Yang wrote:
> >> When resampling irqfds is enabled, level interrupt should be
> >> de-asserted
On Thu, Mar 08, 2018 at 09:49:43AM +, Marc Zyngier wrote:
> [updated Christoffer's email address]
>
> Hi Shunyong,
>
> On 08/03/18 07:01, Shunyong Yang wrote:
> > When resampling irqfds is enabled, level interrupt should be
> > de-asserted when resampling happens. On page 4-47 of GIC v3
> >
Hi Marc,
On 08/03/18 12:54, Marc Zyngier wrote:
> On 08/03/18 09:49, Marc Zyngier wrote:
>> [updated Christoffer's email address]
>>
>> Hi Shunyong,
>>
>> On 08/03/18 07:01, Shunyong Yang wrote:
>>> When resampling irqfds is enabled, level interrupt should be
>>> de-asserted when resampling
On Thu, Mar 08, 2018 at 10:19:49AM +, Marc Zyngier wrote:
> On 07/03/18 23:34, Christoffer Dall wrote:
> > On Wed, Mar 7, 2018 at 12:40 PM, Marc Zyngier wrote:
> >> The vgic code is trying to be clever when injecting GICv2 SGIs,
> >> and will happily populate LRs with
Hi, Eric,
First, please let me change Christoffer's email to cd...@kernel.org. I
add more information about my test below, please check.
On Thu, 2018-03-08 at 09:57 +0100, Auger Eric wrote:
> Hi,
>
> On 08/03/18 08:01, Shunyong Yang wrote:
> >
> > When resampling irqfds is enabled, level
When resampling irqfds is enabled, level interrupt should be
de-asserted when resampling happens. On page 4-47 of GIC v3
specification IHI0069D, it said,
"When the PE acknowledges an SGI, a PPI, or an SPI at the CPU
interface, the IRI changes the status of the interrupt to active
and pending if:
•
Hi Shunyong,
On 08/03/18 10:31, Yang, Shunyong wrote:
> Hi, Eric,
>
> First, please let me change Christoffer's email to cd...@kernel.org. I
> add more information about my test below, please check.
>
> On Thu, 2018-03-08 at 09:57 +0100, Auger Eric wrote:
>> Hi,
>>
>> On 08/03/18 08:01, Shunyong
On Thu, Mar 01, 2018 at 03:55:34PM +, Marc Zyngier wrote:
> So far, the branch from the vector slots to the main vectors can at
> most be 4GB from the main vectors (the reach of ADRP), and this
> distance is known at compile time. If we were to remap the slots
> to an unrelated VA, things
On Thu, Mar 01, 2018 at 03:55:33PM +, Marc Zyngier wrote:
> We are soon going to have to do some extra work in the BP hardening
> vector slots. Instead of doing that work in the vectors themselves
> (which would massively reduce the space available to deal with
> Spectre v2), let's branch to
On 08/03/18 10:19, Marc Zyngier wrote:
> On 07/03/18 23:34, Christoffer Dall wrote:
>> On Wed, Mar 7, 2018 at 12:40 PM, Marc Zyngier wrote:
>>> The vgic code is trying to be clever when injecting GICv2 SGIs,
>>> and will happily populate LRs with the same interrupt number if
On 08/03/18 09:49, Marc Zyngier wrote:
> [updated Christoffer's email address]
>
> Hi Shunyong,
>
> On 08/03/18 07:01, Shunyong Yang wrote:
>> When resampling irqfds is enabled, level interrupt should be
>> de-asserted when resampling happens. On page 4-47 of GIC v3
>> specification IHI0069D, it
On 08/03/18 09:31, Yang, Shunyong wrote:
> Hi, Eric,
>
> First, please let me change Christoffer's email to cd...@kernel.org. I
> add more information about my test below, please check.
>
> On Thu, 2018-03-08 at 09:57 +0100, Auger Eric wrote:
>> Hi,
>>
>> On 08/03/18 08:01, Shunyong Yang wrote:
On Wed, Mar 07, 2018 at 06:15:02PM +, James Morse wrote:
> Today its just x86 and arm64. arm64 doesn't have a hook to do this. I'm happy
> to
> add an empty declaration or leave it under an ifdef until someone complains
> about any behaviour I missed!
So I did some more staring at the code
On 07/03/18 23:34, Christoffer Dall wrote:
> On Wed, Mar 7, 2018 at 12:40 PM, Marc Zyngier wrote:
>> The vgic code is trying to be clever when injecting GICv2 SGIs,
>> and will happily populate LRs with the same interrupt number if
>> they come from multiple vcpus (after
[updated Christoffer's email address]
Hi Shunyong,
On 08/03/18 07:01, Shunyong Yang wrote:
> When resampling irqfds is enabled, level interrupt should be
> de-asserted when resampling happens. On page 4-47 of GIC v3
> specification IHI0069D, it said,
> "When the PE acknowledges an SGI, a PPI, or
Hi,
On 08/03/18 08:01, Shunyong Yang wrote:
> When resampling irqfds is enabled, level interrupt should be
> de-asserted when resampling happens. On page 4-47 of GIC v3
> specification IHI0069D, it said,
> "When the PE acknowledges an SGI, a PPI, or an SPI at the CPU
> interface, the IRI changes
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